Index: kernel/arch/abs32le/include/arch/barrier.h
===================================================================
--- kernel/arch/abs32le/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/abs32le/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -47,6 +47,10 @@
 #define write_barrier()
 
+#ifdef KERNEL
+
 #define smc_coherence(addr)
 #define smc_coherence_block(addr, size)
+
+#endif	/* KERNEL*/
 
 #endif
Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -97,4 +97,6 @@
 #endif
 
+#ifdef KERNEL
+
 /*
  * There are multiple ways ICache can be implemented on ARM machines. Namely
@@ -134,4 +136,5 @@
 #endif
 
+#endif	/* KERNEL */
 
 #endif
Index: kernel/arch/ia32/include/arch/barrier.h
===================================================================
--- kernel/arch/ia32/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/ia32/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -98,4 +98,6 @@
 #endif
 
+#ifdef KERNEL
+
 /*
  * On ia32, the hardware takes care about instruction and data cache coherence,
@@ -107,4 +109,6 @@
 #define smc_coherence_block(a, l)  write_barrier()
 
+#endif	/* KERNEL */
+
 #endif
 
Index: kernel/arch/ia64/include/arch/barrier.h
===================================================================
--- kernel/arch/ia64/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/ia64/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -56,4 +56,6 @@
 	asm volatile (";; sync.i\n" ::: "memory")
 
+#ifdef KERNEL
+
 #define smc_coherence(a)	\
 {				\
@@ -73,4 +75,6 @@
 }
 
+#endif	/* KERNEL */
+
 #endif
 
Index: kernel/arch/mips32/include/arch/barrier.h
===================================================================
--- kernel/arch/mips32/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/mips32/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -46,6 +46,10 @@
 #define write_barrier()  asm volatile ("" ::: "memory")
 
+#ifdef KERNEL
+
 #define smc_coherence(a)
 #define smc_coherence_block(a, l)
+
+#endif	/* KERNEL */
 
 #endif
Index: kernel/arch/ppc32/include/arch/barrier.h
===================================================================
--- kernel/arch/ppc32/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/ppc32/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -51,4 +51,6 @@
 	)
 
+#ifdef KERNEL
+
 #define COHERENCE_INVAL_MIN  4
 
@@ -93,4 +95,6 @@
 }
 
+#endif	/* KERNEL */
+
 #endif
 
Index: kernel/arch/sparc32/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc32/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/sparc32/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -70,6 +70,8 @@
 	)
 
+#ifdef KERNEL
 #define smc_coherence(addr)
 #define smc_coherence_block(addr, size)
+#endif	/* KERNEL */
 
 #endif
Index: kernel/arch/sparc64/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc64/include/arch/barrier.h	(revision b0e014061cbe1c8f1aa804f8e1a40344f95c6af1)
+++ kernel/arch/sparc64/include/arch/barrier.h	(revision 9a08e6bddeb3cffb3e0438813da2a3084dcd33c5)
@@ -116,5 +116,7 @@
 }
 
-#if defined (US)
+#ifdef KERNEL
+
+#if defined(US)
 
 #define FLUSH_INVAL_MIN  4
@@ -151,4 +153,6 @@
 #endif  /* defined(US3) */
 
+#endif	/* KERNEL */
+
 #endif