Index: kernel/arch/sparc64/include/boot/boot.h
===================================================================
--- kernel/arch/sparc64/include/boot/boot.h	(revision 4872160f9c176d257f1757469d1adec8033d95f9)
+++ kernel/arch/sparc64/include/boot/boot.h	(revision 99297424ce4eedf8e36173e2da9cb5d698b9a02b)
@@ -87,5 +87,4 @@
 
 extern memmap_t memmap;
-extern uintptr_t physmem_start;
 
 #endif
Index: kernel/arch/sparc64/include/mm/cache_spec.h
===================================================================
--- kernel/arch/sparc64/include/mm/cache_spec.h	(revision 4872160f9c176d257f1757469d1adec8033d95f9)
+++ kernel/arch/sparc64/include/mm/cache_spec.h	(revision 99297424ce4eedf8e36173e2da9cb5d698b9a02b)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -39,17 +39,19 @@
  * The following macros are valid for the following processors:
  *
- * 	UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
- * 	UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
- * 
+ *  UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
+ *  UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
+ *
  * Should we support other UltraSPARC processors, we need to make sure that
  * the macros are defined correctly for them.
  */
- 
+
 #if defined (US)
-#define DCACHE_SIZE		(16 * 1024)
+	#define DCACHE_SIZE  (16 * 1024)
 #elif defined (US3)
-#define DCACHE_SIZE		(64 * 1024)
+	#define DCACHE_SIZE  (64 * 1024)
 #endif
-#define DCACHE_LINE_SIZE	32	
+
+#define DCACHE_LINE_SIZE  32
+#define DCACHE_TAG_SHIFT  2
 
 #endif