Index: kernel/arch/arm32/src/mach/gta02/gta02.c
===================================================================
--- kernel/arch/arm32/src/mach/gta02/gta02.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ kernel/arch/arm32/src/mach/gta02/gta02.c	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -41,7 +41,7 @@
 #include <genarch/fb/fb.h>
 #include <abi/fb/visuals.h>
-#include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
-#include <genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h>
-#include <genarch/drivers/s3c24xx_timer/s3c24xx_timer.h>
+#include <genarch/drivers/s3c24xx/uart.h>
+#include <genarch/drivers/s3c24xx/irqc.h>
+#include <genarch/drivers/s3c24xx/timer.h>
 #include <genarch/srln/srln.h>
 #include <sysinfo/sysinfo.h>
Index: kernel/genarch/Makefile.inc
===================================================================
--- kernel/genarch/Makefile.inc	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ kernel/genarch/Makefile.inc	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -97,10 +97,10 @@
 ifeq ($(CONFIG_S3C24XX_IRQC),y)
 	GENARCH_SOURCES += \
-		genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c
+		genarch/src/drivers/s3c24xx/irqc.c
 endif
 
 ifeq ($(CONFIG_S3C24XX_UART),y)
 	GENARCH_SOURCES += \
-		genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
+		genarch/src/drivers/s3c24xx/uart.c
 endif
 
Index: kernel/genarch/include/genarch/drivers/s3c24xx/irqc.h
===================================================================
--- kernel/genarch/include/genarch/drivers/s3c24xx/irqc.h	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
+++ kernel/genarch/include/genarch/drivers/s3c24xx/irqc.h	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2010 Jiri Svoboda
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Samsung S3C24xx on-chip interrupt controller driver.
+ */
+
+#ifndef KERN_S3C24XX_IRQC_H_
+#define KERN_S3C24XX_IRQC_H_
+
+#include <typedefs.h>
+
+/** Physical address where S3C24XX Interrupt controller is mapped */
+#define S3C24XX_IRQC_ADDRESS	0x4a000000
+
+/** S3C24xx on-chip interrupt controller registers */
+typedef struct {
+	ioport32_t srcpnd;	/**< Source pending */
+	ioport32_t intmod;	/**< Interrupt mode */
+	ioport32_t intmsk;	/**< Interrupt mask */
+	ioport32_t priority;	/**< Priority */
+	ioport32_t intpnd;	/**< Interrupt pending */
+	ioport32_t intoffset;	/**< Interrupt offset */
+	ioport32_t subsrcpnd;	/**< Sub source pending */
+	ioport32_t intsubmsk;	/** Interrupt sub mask */
+} s3c24xx_irqc_regs_t;
+
+/** S3C24xx Interrupt source numbers.
+ *
+ * These correspond to bit numbers in srcpnd, intmod, intmsk and intpnd
+ * registers as well as to the values read from the intoffset register.
+ */
+enum s3c24xx_int_source {
+	S3C24XX_INT_ADC		= 31,
+	S3C24XX_INT_RTC		= 30,
+	S3C24XX_INT_SPI1	= 29,
+	S3C24XX_INT_UART0	= 28,
+	S3C24XX_INT_IIC		= 27,
+	S3C24XX_INT_USBH	= 26,
+	S3C24XX_INT_USBD	= 25,
+	S3C24XX_INT_NFCON	= 24,
+	S3C24XX_INT_UART1	= 23,
+	S3C24XX_INT_SPI0	= 22,
+	S3C24XX_INT_SDI		= 21,
+	S3C24XX_INT_DMA3	= 20,
+	S3C24XX_INT_DMA2	= 19,
+	S3C24XX_INT_DMA1	= 18,
+	S3C24XX_INT_DMA0	= 17,
+	S3C24XX_INT_LCD		= 16,
+	S3C24XX_INT_UART2	= 15,
+	S3C24XX_INT_TIMER4	= 14,
+	S3C24XX_INT_TIMER3	= 13,
+	S3C24XX_INT_TIMER2	= 12,
+	S3C24XX_INT_TIMER1	= 11,
+	S3C24XX_INT_TIMER0	= 10,
+	S3C24XX_INT_WDT_AC97	= 9,
+	S3C24XX_INT_TICK	= 8,
+	S3C24XX_nBATT_FLT	= 7,
+	S3C24XX_INT_CAM		= 6,
+	S3C24XX_EINT8_23	= 5,
+	S3C24XX_EINT4_7		= 4,
+	S3C24XX_EINT3		= 3,
+	S3C24XX_EINT2		= 2,
+	S3C24XX_EINT1		= 1,
+	S3C24XX_EINT0		= 0
+};
+
+/** S3C24xx Interrupt sub-source numbers.
+ *
+ * These correspond to bit numbers in the intsubmsk register.
+ */
+enum s3c24xx_int_subsource {
+	S3C24XX_SUBINT_AC97	= 14,
+	S3C24XX_SUBINT_WDT	= 13,
+	S3C24XX_SUBINT_CAM_P	= 12,
+	S3C24XX_SUBINT_CAM_C	= 11,
+	S3C24XX_SUBINT_ADC_S	= 10,
+	S3C24XX_SUBINT_TC	= 9,
+	S3C24XX_SUBINT_ERR2	= 8,
+	S3C24XX_SUBINT_TXD2	= 7,
+	S3C24XX_SUBINT_RXD2	= 6,
+	S3C24XX_SUBINT_ERR1	= 5,
+	S3C24XX_SUBINT_TXD1	= 4,
+	S3C24XX_SUBINT_RXD1	= 3,
+	S3C24XX_SUBINT_ERR0	= 2,
+	S3C24XX_SUBINT_TXD0	= 1,
+	S3C24XX_SUBINT_RXD0	= 0
+};
+
+#define S3C24XX_INT_BIT(source) (1 << (source))
+#define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource))
+
+typedef struct {
+	s3c24xx_irqc_regs_t *regs;
+} s3c24xx_irqc_t;
+
+extern void s3c24xx_irqc_init(s3c24xx_irqc_t *, s3c24xx_irqc_regs_t *);
+extern unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *);
+extern void s3c24xx_irqc_clear(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *, unsigned);
+
+#endif
+
+/** @}
+ */
Index: kernel/genarch/include/genarch/drivers/s3c24xx/timer.h
===================================================================
--- kernel/genarch/include/genarch/drivers/s3c24xx/timer.h	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
+++ kernel/genarch/include/genarch/drivers/s3c24xx/timer.h	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2010 Jiri Svoboda
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Samsung S3C24xx on-chip PWM timer driver.
+ */
+
+#ifndef KERN_S3C24XX_TIMER_H_
+#define KERN_S3C24XX_TIMER_H_
+
+#include <typedefs.h>
+
+/** Physical address where S3C24XX on-chip PWM timer is mapped */
+#define S3C24XX_TIMER_ADDRESS	0x51000000
+
+/** S3C24xx on-chip PWM timer registers */
+typedef struct {
+	ioport32_t tcfg0;	/**< Timer configuration register 0 */
+	ioport32_t tcfg1;	/**< Timer configuration register 1 */
+	ioport32_t tcon;	/**< Timer control register */
+
+	struct {
+		ioport32_t cntb;	/**< Count buffer register */
+		ioport32_t cmpb;	/**< Compare buffer register */
+		ioport32_t cnto;	/**< Count observation register */
+	} timer[5];
+} s3c24xx_timer_t;
+
+/** Bits in the S3C24xx PWM timer TCON register. */
+enum s3c24xx_tcon_bits {
+	TCON_T0_START		= (1 << 0),	/**< Timer 0 start */
+	TCON_T0_MUPDATE		= (1 << 1),	/**< Timer 0 manual update */
+	TCON_T0_INVERT		= (1 << 2),	/**< Timer 0 inverter on */
+	TCON_T0_AUTO_RLD	= (1 << 3),	/**< Timer 0 auto reload */
+
+	TCON_DEAD_ZONE		= (1 << 4),	/**< Dead zone enable */
+
+	TCON_T1_START		= (1 << 8),	/**< Timer 1 start */
+	TCON_T1_MUPDATE		= (1 << 9),	/**< Timer 1 manual update */
+	TCON_T1_INVERT		= (1 << 10),	/**< Timer 1 inverter on */
+	TCON_T1_AUTO_RLD	= (1 << 11),	/**< Timer 1 auto reload */
+
+	TCON_T2_START		= (1 << 12),	/**< Timer 2 start */
+	TCON_T2_MUPDATE		= (1 << 13),	/**< Timer 2 manual update */
+	TCON_T2_INVERT		= (1 << 14),	/**< Timer 2 inverter on */
+	TCON_T2_AUTO_RLD	= (1 << 15),	/**< Timer 2 auto reload */
+
+	TCON_T3_START		= (1 << 16),	/**< Timer 3 start */
+	TCON_T3_MUPDATE		= (1 << 17),	/**< Timer 3 manual update */
+	TCON_T3_INVERT		= (1 << 18),	/**< Timer 3 inverter on */
+	TCON_T3_AUTO_RLD	= (1 << 19),	/**< Timer 3 auto reload */
+
+	TCON_T4_START		= (1 << 20),	/**< Timer 4 start */
+	TCON_T4_MUPDATE		= (1 << 21),	/**< Timer 4 manual update */
+	TCON_T4_AUTO_RLD	= (1 << 22)	/**< Timer 4 auto reload */
+};
+
+#endif
+
+/** @}
+ */
Index: kernel/genarch/include/genarch/drivers/s3c24xx/uart.h
===================================================================
--- kernel/genarch/include/genarch/drivers/s3c24xx/uart.h	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
+++ kernel/genarch/include/genarch/drivers/s3c24xx/uart.h	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2010 Jiri Svoboda
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Samsung S3C24xx on-chip UART driver.
+ */
+
+#ifndef KERN_S3C24XX_UART_H_
+#define KERN_S3C24XX_UART_H_
+
+#include <ddi/ddi.h>
+#include <ddi/irq.h>
+#include <console/chardev.h>
+#include <typedefs.h>
+
+/** S3C24xx UART I/O */
+typedef struct {
+	uint32_t ulcon;
+	uint32_t ucon;
+	uint32_t ufcon;
+	uint32_t umcon;
+
+	uint32_t utrstat;
+	uint32_t uerstat;
+	uint32_t ufstat;
+	uint32_t umstat;
+
+	uint32_t utxh;
+	uint32_t urxh;
+
+	uint32_t ubrdiv;
+} s3c24xx_uart_io_t;
+
+/* Bits in UTRSTAT register */
+#define S3C24XX_UTRSTAT_TX_EMPTY	0x4
+#define S3C24XX_UTRSTAT_RDATA		0x1
+
+/* Bits in UFSTAT register */
+#define S3C24XX_UFSTAT_TX_FULL		0x4000
+#define S3C24XX_UFSTAT_RX_FULL		0x0040
+#define S3C24XX_UFSTAT_RX_COUNT		0x002f
+
+/* Bits in UCON register */
+#define UCON_RX_INT_LEVEL		0x100
+
+/* Bits in UFCON register */
+#define UFCON_TX_FIFO_TLEVEL_EMPTY	0x00
+#define UFCON_RX_FIFO_TLEVEL_1B		0x00
+#define UFCON_FIFO_ENABLE		0x01
+
+
+/** S3C24xx UART instance */
+typedef struct {
+	s3c24xx_uart_io_t *io;
+	indev_t *indev;
+	irq_t irq;
+	parea_t parea;
+} s3c24xx_uart_t;
+
+extern outdev_t *s3c24xx_uart_init(uintptr_t, inr_t inr);
+extern void s3c24xx_uart_input_wire(s3c24xx_uart_t *,
+    indev_t *);
+
+#endif
+
+/** @}
+ */
Index: rnel/genarch/include/genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h
===================================================================
--- kernel/genarch/include/genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ 	(revision )
@@ -1,137 +1,0 @@
-/*
- * Copyright (c) 2010 Jiri Svoboda
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Samsung S3C24xx on-chip interrupt controller driver.
- */
-
-#ifndef KERN_S3C24XX_IRQC_H_
-#define KERN_S3C24XX_IRQC_H_
-
-#include <typedefs.h>
-
-/** Physical address where S3C24XX Interrupt controller is mapped */
-#define S3C24XX_IRQC_ADDRESS	0x4a000000
-
-/** S3C24xx on-chip interrupt controller registers */
-typedef struct {
-	ioport32_t srcpnd;	/**< Source pending */
-	ioport32_t intmod;	/**< Interrupt mode */
-	ioport32_t intmsk;	/**< Interrupt mask */
-	ioport32_t priority;	/**< Priority */
-	ioport32_t intpnd;	/**< Interrupt pending */
-	ioport32_t intoffset;	/**< Interrupt offset */
-	ioport32_t subsrcpnd;	/**< Sub source pending */
-	ioport32_t intsubmsk;	/** Interrupt sub mask */
-} s3c24xx_irqc_regs_t;
-
-/** S3C24xx Interrupt source numbers.
- *
- * These correspond to bit numbers in srcpnd, intmod, intmsk and intpnd
- * registers as well as to the values read from the intoffset register.
- */
-enum s3c24xx_int_source {
-	S3C24XX_INT_ADC		= 31,
-	S3C24XX_INT_RTC		= 30,
-	S3C24XX_INT_SPI1	= 29,
-	S3C24XX_INT_UART0	= 28,
-	S3C24XX_INT_IIC		= 27,
-	S3C24XX_INT_USBH	= 26,
-	S3C24XX_INT_USBD	= 25,
-	S3C24XX_INT_NFCON	= 24,
-	S3C24XX_INT_UART1	= 23,
-	S3C24XX_INT_SPI0	= 22,
-	S3C24XX_INT_SDI		= 21,
-	S3C24XX_INT_DMA3	= 20,
-	S3C24XX_INT_DMA2	= 19,
-	S3C24XX_INT_DMA1	= 18,
-	S3C24XX_INT_DMA0	= 17,
-	S3C24XX_INT_LCD		= 16,
-	S3C24XX_INT_UART2	= 15,
-	S3C24XX_INT_TIMER4	= 14,
-	S3C24XX_INT_TIMER3	= 13,
-	S3C24XX_INT_TIMER2	= 12,
-	S3C24XX_INT_TIMER1	= 11,
-	S3C24XX_INT_TIMER0	= 10,
-	S3C24XX_INT_WDT_AC97	= 9,
-	S3C24XX_INT_TICK	= 8,
-	S3C24XX_nBATT_FLT	= 7,
-	S3C24XX_INT_CAM		= 6,
-	S3C24XX_EINT8_23	= 5,
-	S3C24XX_EINT4_7		= 4,
-	S3C24XX_EINT3		= 3,
-	S3C24XX_EINT2		= 2,
-	S3C24XX_EINT1		= 1,
-	S3C24XX_EINT0		= 0
-};
-
-/** S3C24xx Interrupt sub-source numbers.
- *
- * These correspond to bit numbers in the intsubmsk register.
- */
-enum s3c24xx_int_subsource {
-	S3C24XX_SUBINT_AC97	= 14,
-	S3C24XX_SUBINT_WDT	= 13,
-	S3C24XX_SUBINT_CAM_P	= 12,
-	S3C24XX_SUBINT_CAM_C	= 11,
-	S3C24XX_SUBINT_ADC_S	= 10,
-	S3C24XX_SUBINT_TC	= 9,
-	S3C24XX_SUBINT_ERR2	= 8,
-	S3C24XX_SUBINT_TXD2	= 7,
-	S3C24XX_SUBINT_RXD2	= 6,
-	S3C24XX_SUBINT_ERR1	= 5,
-	S3C24XX_SUBINT_TXD1	= 4,
-	S3C24XX_SUBINT_RXD1	= 3,
-	S3C24XX_SUBINT_ERR0	= 2,
-	S3C24XX_SUBINT_TXD0	= 1,
-	S3C24XX_SUBINT_RXD0	= 0
-};
-
-#define S3C24XX_INT_BIT(source) (1 << (source))
-#define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource))
-
-typedef struct {
-	s3c24xx_irqc_regs_t *regs;
-} s3c24xx_irqc_t;
-
-extern void s3c24xx_irqc_init(s3c24xx_irqc_t *, s3c24xx_irqc_regs_t *);
-extern unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *);
-extern void s3c24xx_irqc_clear(s3c24xx_irqc_t *, unsigned);
-extern void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *, unsigned);
-extern void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *, unsigned);
-extern void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *, unsigned);
-extern void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *, unsigned);
-
-#endif
-
-/** @}
- */
Index: rnel/genarch/include/genarch/drivers/s3c24xx_timer/s3c24xx_timer.h
===================================================================
--- kernel/genarch/include/genarch/drivers/s3c24xx_timer/s3c24xx_timer.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ 	(revision )
@@ -1,90 +1,0 @@
-/*
- * Copyright (c) 2010 Jiri Svoboda
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Samsung S3C24xx on-chip PWM timer driver.
- */
-
-#ifndef KERN_S3C24XX_TIMER_H_
-#define KERN_S3C24XX_TIMER_H_
-
-#include <typedefs.h>
-
-/** Physical address where S3C24XX on-chip PWM timer is mapped */
-#define S3C24XX_TIMER_ADDRESS	0x51000000
-
-/** S3C24xx on-chip PWM timer registers */
-typedef struct {
-	ioport32_t tcfg0;	/**< Timer configuration register 0 */
-	ioport32_t tcfg1;	/**< Timer configuration register 1 */
-	ioport32_t tcon;	/**< Timer control register */
-
-	struct {
-		ioport32_t cntb;	/**< Count buffer register */
-		ioport32_t cmpb;	/**< Compare buffer register */
-		ioport32_t cnto;	/**< Count observation register */
-	} timer[5];
-} s3c24xx_timer_t;
-
-/** Bits in the S3C24xx PWM timer TCON register. */
-enum s3c24xx_tcon_bits {
-	TCON_T0_START		= (1 << 0),	/**< Timer 0 start */
-	TCON_T0_MUPDATE		= (1 << 1),	/**< Timer 0 manual update */
-	TCON_T0_INVERT		= (1 << 2),	/**< Timer 0 inverter on */
-	TCON_T0_AUTO_RLD	= (1 << 3),	/**< Timer 0 auto reload */
-
-	TCON_DEAD_ZONE		= (1 << 4),	/**< Dead zone enable */
-
-	TCON_T1_START		= (1 << 8),	/**< Timer 1 start */
-	TCON_T1_MUPDATE		= (1 << 9),	/**< Timer 1 manual update */
-	TCON_T1_INVERT		= (1 << 10),	/**< Timer 1 inverter on */
-	TCON_T1_AUTO_RLD	= (1 << 11),	/**< Timer 1 auto reload */
-
-	TCON_T2_START		= (1 << 12),	/**< Timer 2 start */
-	TCON_T2_MUPDATE		= (1 << 13),	/**< Timer 2 manual update */
-	TCON_T2_INVERT		= (1 << 14),	/**< Timer 2 inverter on */
-	TCON_T2_AUTO_RLD	= (1 << 15),	/**< Timer 2 auto reload */
-
-	TCON_T3_START		= (1 << 16),	/**< Timer 3 start */
-	TCON_T3_MUPDATE		= (1 << 17),	/**< Timer 3 manual update */
-	TCON_T3_INVERT		= (1 << 18),	/**< Timer 3 inverter on */
-	TCON_T3_AUTO_RLD	= (1 << 19),	/**< Timer 3 auto reload */
-
-	TCON_T4_START		= (1 << 20),	/**< Timer 4 start */
-	TCON_T4_MUPDATE		= (1 << 21),	/**< Timer 4 manual update */
-	TCON_T4_AUTO_RLD	= (1 << 22)	/**< Timer 4 auto reload */
-};
-
-#endif
-
-/** @}
- */
Index: rnel/genarch/include/genarch/drivers/s3c24xx_uart/s3c24xx_uart.h
===================================================================
--- kernel/genarch/include/genarch/drivers/s3c24xx_uart/s3c24xx_uart.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ 	(revision )
@@ -1,96 +1,0 @@
-/*
- * Copyright (c) 2010 Jiri Svoboda
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Samsung S3C24xx on-chip UART driver.
- */
-
-#ifndef KERN_S3C24XX_UART_H_
-#define KERN_S3C24XX_UART_H_
-
-#include <ddi/ddi.h>
-#include <ddi/irq.h>
-#include <console/chardev.h>
-#include <typedefs.h>
-
-/** S3C24xx UART I/O */
-typedef struct {
-	uint32_t ulcon;
-	uint32_t ucon;
-	uint32_t ufcon;
-	uint32_t umcon;
-
-	uint32_t utrstat;
-	uint32_t uerstat;
-	uint32_t ufstat;
-	uint32_t umstat;
-
-	uint32_t utxh;
-	uint32_t urxh;
-
-	uint32_t ubrdiv;
-} s3c24xx_uart_io_t;
-
-/* Bits in UTRSTAT register */
-#define S3C24XX_UTRSTAT_TX_EMPTY	0x4
-#define S3C24XX_UTRSTAT_RDATA		0x1
-
-/* Bits in UFSTAT register */
-#define S3C24XX_UFSTAT_TX_FULL		0x4000
-#define S3C24XX_UFSTAT_RX_FULL		0x0040
-#define S3C24XX_UFSTAT_RX_COUNT		0x002f
-
-/* Bits in UCON register */
-#define UCON_RX_INT_LEVEL		0x100
-
-/* Bits in UFCON register */
-#define UFCON_TX_FIFO_TLEVEL_EMPTY	0x00
-#define UFCON_RX_FIFO_TLEVEL_1B		0x00
-#define UFCON_FIFO_ENABLE		0x01
-
-
-/** S3C24xx UART instance */
-typedef struct {
-	s3c24xx_uart_io_t *io;
-	indev_t *indev;
-	irq_t irq;
-	parea_t parea;
-} s3c24xx_uart_t;
-
-extern outdev_t *s3c24xx_uart_init(uintptr_t, inr_t inr);
-extern void s3c24xx_uart_input_wire(s3c24xx_uart_t *,
-    indev_t *);
-
-#endif
-
-/** @}
- */
Index: kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c
===================================================================
--- kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -37,5 +37,4 @@
 #include <genarch/drivers/grlib_irqmp/grlib_irqmp.h>
 #include <arch/asm.h>
-
 #include <mm/km.h>
 
Index: kernel/genarch/src/drivers/s3c24xx/irqc.c
===================================================================
--- kernel/genarch/src/drivers/s3c24xx/irqc.c	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
+++ kernel/genarch/src/drivers/s3c24xx/irqc.c	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2010 Jiri Svoboda
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Samsung S3C24xx on-chip interrupt controller.
+ *
+ * This IRQC is present on the Samsung S3C24xx CPU (on the gta02 platform).
+ */
+
+#include <genarch/drivers/s3c24xx/irqc.h>
+#include <arch/asm.h>
+
+/** Correspondence between interrupt sources and sub-sources. */
+static unsigned s3c24xx_subsrc_src[][2] = {
+	{ S3C24XX_SUBINT_CAM_P, S3C24XX_INT_CAM },
+	{ S3C24XX_SUBINT_CAM_C, S3C24XX_INT_CAM },
+	{ S3C24XX_SUBINT_ADC_S, S3C24XX_INT_ADC },
+	{ S3C24XX_SUBINT_TC, S3C24XX_INT_ADC },
+	{ S3C24XX_SUBINT_ERR2, S3C24XX_INT_UART2 },
+	{ S3C24XX_SUBINT_TXD2, S3C24XX_INT_UART2 },
+	{ S3C24XX_SUBINT_RXD2, S3C24XX_INT_UART2 },
+	{ S3C24XX_SUBINT_ERR1, S3C24XX_INT_UART1 },
+	{ S3C24XX_SUBINT_TXD1, S3C24XX_INT_UART1 },
+	{ S3C24XX_SUBINT_RXD1, S3C24XX_INT_UART1 },
+	{ S3C24XX_SUBINT_ERR0, S3C24XX_INT_UART0 },
+	{ S3C24XX_SUBINT_TXD0, S3C24XX_INT_UART0 },
+	{ S3C24XX_SUBINT_RXD0, S3C24XX_INT_UART0 }
+};
+
+/** Initialize S3C24xx interrupt controller.
+ *
+ * @param irqc	Instance structure
+ * @param regs	Register I/O structure
+ */
+void s3c24xx_irqc_init(s3c24xx_irqc_t *irqc, s3c24xx_irqc_regs_t *regs)
+{
+	irqc->regs = regs;
+
+	/* Make all interrupt sources use IRQ mode (not FIQ). */
+	pio_write_32(&regs->intmod, 0x00000000);
+
+	/* Disable all interrupt sources. */
+	pio_write_32(&regs->intmsk, 0xffffffff);
+
+	/* Disable interrupts from all sub-sources. */
+	pio_write_32(&regs->intsubmsk, 0xffffffff);
+}
+
+/** Obtain number of pending interrupt. */
+unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *irqc)
+{
+	return pio_read_32(&irqc->regs->intoffset);
+}
+
+/** Clear pending interrupt condition including sub-sources.
+ *
+ * Clear source and interrupt pending condition and also automatically clear
+ * any sub-source pending condition pertaining to the source.
+ */
+void s3c24xx_irqc_clear(s3c24xx_irqc_t *irqc, unsigned inum)
+{
+	unsigned src, subsrc;
+	unsigned entries, i;
+
+	entries = sizeof(s3c24xx_subsrc_src) / sizeof(s3c24xx_subsrc_src[0]);
+
+	for (i = 0; i < entries; i++) {
+		subsrc = s3c24xx_subsrc_src[i][0];
+		src = s3c24xx_subsrc_src[i][1];
+
+		if (src == inum) {
+			pio_write_32(&irqc->regs->subsrcpnd,
+			    S3C24XX_SUBINT_BIT(subsrc));
+		}
+	}
+
+	pio_write_32(&irqc->regs->srcpnd, S3C24XX_INT_BIT(inum));
+	pio_write_32(&irqc->regs->intpnd, S3C24XX_INT_BIT(inum));
+}
+
+/** Enable interrupts from the specified source. */
+void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *irqc, unsigned src)
+{
+	pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) &
+	    ~S3C24XX_INT_BIT(src));
+}
+
+/** Disable interrupts from the specified source. */
+void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *irqc, unsigned src)
+{
+	pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) |
+	    S3C24XX_INT_BIT(src));
+}
+
+/** Enable interrupts from the specified sub-source. */
+void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *irqc, unsigned subsrc)
+{
+	pio_write_32(&irqc->regs->intsubmsk,
+	    pio_read_32(&irqc->regs->intsubmsk) &
+	    ~S3C24XX_SUBINT_BIT(subsrc));
+}
+
+/** Disable interrupts from the specified sub-source. */
+void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *irqc, unsigned subsrc)
+{
+	pio_write_32(&irqc->regs->intsubmsk,
+	    pio_read_32(&irqc->regs->intsubmsk) |
+	    S3C24XX_SUBINT_BIT(subsrc));
+}
+
+/** @}
+ */
Index: kernel/genarch/src/drivers/s3c24xx/uart.c
===================================================================
--- kernel/genarch/src/drivers/s3c24xx/uart.c	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
+++ kernel/genarch/src/drivers/s3c24xx/uart.c	(revision 96b972427511fafc3a7d22675c4ad68162b5f167)
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2009 Martin Decky
+ * Copyright (c) 2010 Jiri Svoboda
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Samsung S3C24xx on-chip UART driver.
+ *
+ * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
+ */
+
+#include <genarch/drivers/s3c24xx/uart.h>
+#include <console/chardev.h>
+#include <console/console.h>
+#include <ddi/device.h>
+#include <arch/asm.h>
+#include <mm/slab.h>
+#include <mm/page.h>
+#include <mm/km.h>
+#include <sysinfo/sysinfo.h>
+#include <str.h>
+
+static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
+{
+	s3c24xx_uart_t *uart =
+	    (s3c24xx_uart_t *) dev->data;
+
+	/* Wait for space becoming available in Tx FIFO. */
+	while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
+		;
+
+	pio_write_32(&uart->io->utxh, byte);
+}
+
+static void s3c24xx_uart_putchar(outdev_t *dev, wchar_t ch)
+{
+	s3c24xx_uart_t *uart =
+	    (s3c24xx_uart_t *) dev->data;
+	
+	if ((!uart->parea.mapped) || (console_override)) {
+		if (!ascii_check(ch)) {
+			s3c24xx_uart_sendb(dev, U_SPECIAL);
+		} else {
+			if (ch == '\n')
+				s3c24xx_uart_sendb(dev, (uint8_t) '\r');
+			s3c24xx_uart_sendb(dev, (uint8_t) ch);
+		}
+	}
+}
+
+static irq_ownership_t s3c24xx_uart_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void s3c24xx_uart_irq_handler(irq_t *irq)
+{
+	s3c24xx_uart_t *uart = irq->instance;
+
+	while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
+		uint32_t data = pio_read_32(&uart->io->urxh);
+		pio_read_32(&uart->io->uerstat);
+		indev_push_character(uart->indev, data & 0xff);
+	}
+}
+
+static outdev_operations_t s3c24xx_uart_ops = {
+	.write = s3c24xx_uart_putchar,
+	.redraw = NULL
+};
+
+outdev_t *s3c24xx_uart_init(uintptr_t paddr, inr_t inr)
+{
+	outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
+	if (!uart_dev)
+		return NULL;
+
+	s3c24xx_uart_t *uart =
+	    malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC);
+	if (!uart) {
+		free(uart_dev);
+		return NULL;
+	}
+
+	outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops);
+	uart_dev->data = uart;
+
+	uart->io = (s3c24xx_uart_io_t *) km_map(paddr, PAGE_SIZE,
+	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
+	uart->indev = NULL;
+
+	/* Initialize IRQ structure. */
+	irq_initialize(&uart->irq);
+	uart->irq.devno = device_assign_devno();
+	uart->irq.inr = inr;
+	uart->irq.claim = s3c24xx_uart_claim;
+	uart->irq.handler = s3c24xx_uart_irq_handler;
+	uart->irq.instance = uart;
+
+	/* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
+	pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
+	    UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
+
+	/* Set RX interrupt to pulse mode */
+	pio_write_32(&uart->io->ucon,
+	    pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
+	
+	link_initialize(&uart->parea.link);
+	uart->parea.pbase = paddr;
+	uart->parea.frames = 1;
+	uart->parea.unpriv = false;
+	uart->parea.mapped = false;
+	ddi_parea_register(&uart->parea);
+	
+	if (!fb_exported) {
+		/*
+		 * This is the necessary evil until
+		 * the userspace driver is entirely
+		 * self-sufficient.
+		 */
+		sysinfo_set_item_val("fb", NULL, true);
+		sysinfo_set_item_val("fb.kind", NULL, 3);
+		sysinfo_set_item_val("fb.address.physical", NULL, paddr);
+
+		fb_exported = true;
+	}
+
+	return uart_dev;
+}
+
+void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev)
+{
+	ASSERT(uart);
+	ASSERT(indev);
+
+	uart->indev = indev;
+	irq_register(&uart->irq);
+}
+
+/** @}
+ */
Index: rnel/genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c
===================================================================
--- kernel/genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ 	(revision )
@@ -1,141 +1,0 @@
-/*
- * Copyright (c) 2010 Jiri Svoboda
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Samsung S3C24xx on-chip interrupt controller.
- *
- * This IRQC is present on the Samsung S3C24xx CPU (on the gta02 platform).
- */
-
-#include <genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h>
-#include <arch/asm.h>
-
-/** Correspondence between interrupt sources and sub-sources. */
-static unsigned s3c24xx_subsrc_src[][2] = {
-	{ S3C24XX_SUBINT_CAM_P, S3C24XX_INT_CAM },
-	{ S3C24XX_SUBINT_CAM_C, S3C24XX_INT_CAM },
-	{ S3C24XX_SUBINT_ADC_S, S3C24XX_INT_ADC },
-	{ S3C24XX_SUBINT_TC, S3C24XX_INT_ADC },
-	{ S3C24XX_SUBINT_ERR2, S3C24XX_INT_UART2 },
-	{ S3C24XX_SUBINT_TXD2, S3C24XX_INT_UART2 },
-	{ S3C24XX_SUBINT_RXD2, S3C24XX_INT_UART2 },
-	{ S3C24XX_SUBINT_ERR1, S3C24XX_INT_UART1 },
-	{ S3C24XX_SUBINT_TXD1, S3C24XX_INT_UART1 },
-	{ S3C24XX_SUBINT_RXD1, S3C24XX_INT_UART1 },
-	{ S3C24XX_SUBINT_ERR0, S3C24XX_INT_UART0 },
-	{ S3C24XX_SUBINT_TXD0, S3C24XX_INT_UART0 },
-	{ S3C24XX_SUBINT_RXD0, S3C24XX_INT_UART0 }
-};
-
-/** Initialize S3C24xx interrupt controller.
- *
- * @param irqc	Instance structure
- * @param regs	Register I/O structure
- */
-void s3c24xx_irqc_init(s3c24xx_irqc_t *irqc, s3c24xx_irqc_regs_t *regs)
-{
-	irqc->regs = regs;
-
-	/* Make all interrupt sources use IRQ mode (not FIQ). */
-	pio_write_32(&regs->intmod, 0x00000000);
-
-	/* Disable all interrupt sources. */
-	pio_write_32(&regs->intmsk, 0xffffffff);
-
-	/* Disable interrupts from all sub-sources. */
-	pio_write_32(&regs->intsubmsk, 0xffffffff);
-}
-
-/** Obtain number of pending interrupt. */
-unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *irqc)
-{
-	return pio_read_32(&irqc->regs->intoffset);
-}
-
-/** Clear pending interrupt condition including sub-sources.
- *
- * Clear source and interrupt pending condition and also automatically clear
- * any sub-source pending condition pertaining to the source.
- */
-void s3c24xx_irqc_clear(s3c24xx_irqc_t *irqc, unsigned inum)
-{
-	unsigned src, subsrc;
-	unsigned entries, i;
-
-	entries = sizeof(s3c24xx_subsrc_src) / sizeof(s3c24xx_subsrc_src[0]);
-
-	for (i = 0; i < entries; i++) {
-		subsrc = s3c24xx_subsrc_src[i][0];
-		src = s3c24xx_subsrc_src[i][1];
-
-		if (src == inum) {
-			pio_write_32(&irqc->regs->subsrcpnd,
-			    S3C24XX_SUBINT_BIT(subsrc));
-		}
-	}
-
-	pio_write_32(&irqc->regs->srcpnd, S3C24XX_INT_BIT(inum));
-	pio_write_32(&irqc->regs->intpnd, S3C24XX_INT_BIT(inum));
-}
-
-/** Enable interrupts from the specified source. */
-void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *irqc, unsigned src)
-{
-	pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) &
-	    ~S3C24XX_INT_BIT(src));
-}
-
-/** Disable interrupts from the specified source. */
-void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *irqc, unsigned src)
-{
-	pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) |
-	    S3C24XX_INT_BIT(src));
-}
-
-/** Enable interrupts from the specified sub-source. */
-void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *irqc, unsigned subsrc)
-{
-	pio_write_32(&irqc->regs->intsubmsk,
-	    pio_read_32(&irqc->regs->intsubmsk) &
-	    ~S3C24XX_SUBINT_BIT(subsrc));
-}
-
-/** Disable interrupts from the specified sub-source. */
-void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *irqc, unsigned subsrc)
-{
-	pio_write_32(&irqc->regs->intsubmsk,
-	    pio_read_32(&irqc->regs->intsubmsk) |
-	    S3C24XX_SUBINT_BIT(subsrc));
-}
-
-/** @}
- */
Index: rnel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
===================================================================
--- kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
+++ 	(revision )
@@ -1,169 +1,0 @@
-/*
- * Copyright (c) 2009 Martin Decky
- * Copyright (c) 2010 Jiri Svoboda
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Samsung S3C24xx on-chip UART driver.
- *
- * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform).
- */
-
-#include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
-#include <console/chardev.h>
-#include <console/console.h>
-#include <ddi/device.h>
-#include <arch/asm.h>
-#include <mm/slab.h>
-#include <mm/page.h>
-#include <mm/km.h>
-#include <sysinfo/sysinfo.h>
-#include <str.h>
-
-static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
-{
-	s3c24xx_uart_t *uart =
-	    (s3c24xx_uart_t *) dev->data;
-
-	/* Wait for space becoming available in Tx FIFO. */
-	while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
-		;
-
-	pio_write_32(&uart->io->utxh, byte);
-}
-
-static void s3c24xx_uart_putchar(outdev_t *dev, wchar_t ch)
-{
-	s3c24xx_uart_t *uart =
-	    (s3c24xx_uart_t *) dev->data;
-	
-	if ((!uart->parea.mapped) || (console_override)) {
-		if (!ascii_check(ch)) {
-			s3c24xx_uart_sendb(dev, U_SPECIAL);
-		} else {
-			if (ch == '\n')
-				s3c24xx_uart_sendb(dev, (uint8_t) '\r');
-			s3c24xx_uart_sendb(dev, (uint8_t) ch);
-		}
-	}
-}
-
-static irq_ownership_t s3c24xx_uart_claim(irq_t *irq)
-{
-	return IRQ_ACCEPT;
-}
-
-static void s3c24xx_uart_irq_handler(irq_t *irq)
-{
-	s3c24xx_uart_t *uart = irq->instance;
-
-	while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
-		uint32_t data = pio_read_32(&uart->io->urxh);
-		pio_read_32(&uart->io->uerstat);
-		indev_push_character(uart->indev, data & 0xff);
-	}
-}
-
-static outdev_operations_t s3c24xx_uart_ops = {
-	.write = s3c24xx_uart_putchar,
-	.redraw = NULL
-};
-
-outdev_t *s3c24xx_uart_init(uintptr_t paddr, inr_t inr)
-{
-	outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
-	if (!uart_dev)
-		return NULL;
-
-	s3c24xx_uart_t *uart =
-	    malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC);
-	if (!uart) {
-		free(uart_dev);
-		return NULL;
-	}
-
-	outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops);
-	uart_dev->data = uart;
-
-	uart->io = (s3c24xx_uart_io_t *) km_map(paddr, PAGE_SIZE,
-	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
-	uart->indev = NULL;
-
-	/* Initialize IRQ structure. */
-	irq_initialize(&uart->irq);
-	uart->irq.devno = device_assign_devno();
-	uart->irq.inr = inr;
-	uart->irq.claim = s3c24xx_uart_claim;
-	uart->irq.handler = s3c24xx_uart_irq_handler;
-	uart->irq.instance = uart;
-
-	/* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
-	pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
-	    UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
-
-	/* Set RX interrupt to pulse mode */
-	pio_write_32(&uart->io->ucon,
-	    pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
-	
-	link_initialize(&uart->parea.link);
-	uart->parea.pbase = paddr;
-	uart->parea.frames = 1;
-	uart->parea.unpriv = false;
-	uart->parea.mapped = false;
-	ddi_parea_register(&uart->parea);
-	
-	if (!fb_exported) {
-		/*
-		 * This is the necessary evil until
-		 * the userspace driver is entirely
-		 * self-sufficient.
-		 */
-		sysinfo_set_item_val("fb", NULL, true);
-		sysinfo_set_item_val("fb.kind", NULL, 3);
-		sysinfo_set_item_val("fb.address.physical", NULL, paddr);
-
-		fb_exported = true;
-	}
-
-	return uart_dev;
-}
-
-void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev)
-{
-	ASSERT(uart);
-	ASSERT(indev);
-
-	uart->indev = indev;
-	irq_register(&uart->irq);
-}
-
-/** @}
- */
