Index: kernel/arch/sparc64/include/arch.h
===================================================================
--- kernel/arch/sparc64/include/arch.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/arch.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -42,5 +42,5 @@
 #define ASI_NUCLEUS_QUAD_LDD	0x24	/** ASI for 16-byte atomic loads. */
 #define ASI_DCACHE_TAG		0x47	/** ASI D-Cache Tag. */
-#define ASI_UPA_CONFIG		0x4a	/** ASI of the UPA_CONFIG register. */
+#define ASI_ICBUS_CONFIG		0x4a	/** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
 
 #define NWINDOWS		8	/** Number of register window sets. */
Index: kernel/arch/sparc64/include/asm.h
===================================================================
--- kernel/arch/sparc64/include/asm.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/asm.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -137,4 +137,26 @@
 }
 
+/** Read STICK_compare Register.
+ *
+ * @return Value of STICK_compare register.
+ */
+static inline uint64_t stick_compare_read(void)
+{
+	uint64_t v;
+	
+	asm volatile ("rd %%asr25, %0\n" : "=r" (v));
+	
+	return v;
+}
+
+/** Write STICK_compare Register.
+ *
+ * @param v New value of STICK_comapre register.
+ */
+static inline void stick_compare_write(uint64_t v)
+{
+	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
+}
+
 /** Read TICK Register.
  *
@@ -408,13 +430,4 @@
 }
 
-/** Read UPA_CONFIG register.
- *
- * @return Value of the UPA_CONFIG register.
- */
-static inline uint64_t upa_config_read(void)
-{
-	return asi_u64_read(ASI_UPA_CONFIG, 0);
-}
-
 extern void cpu_halt(void);
 extern void cpu_sleep(void);
Index: kernel/arch/sparc64/include/cpu.h
===================================================================
--- kernel/arch/sparc64/include/cpu.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/cpu.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -36,13 +36,4 @@
 #define KERN_sparc64_CPU_H_
 
-#include <arch/types.h>
-#include <typedefs.h>
-#include <arch/register.h>
-#include <arch/asm.h>
-
-#ifdef CONFIG_SMP
-#include <arch/mm/cache.h>
-#endif
-
 #define MANUF_FUJITSU		0x04
 #define MANUF_ULTRASPARC	0x17	/**< UltraSPARC I, UltraSPARC II */
@@ -53,12 +44,27 @@
 #define IMPL_ULTRASPARCII_I	0x12
 #define IMPL_ULTRASPARCII_E	0x13
-#define IMPL_ULTRASPARCIII	0x15
+#define IMPL_ULTRASPARCIII	0x14
+#define IMPL_ULTRASPARCIII_PLUS	0x15
+#define IMPL_ULTRASPARCIII_I	0x16
+#define IMPL_ULTRASPARCIV	0x18
 #define IMPL_ULTRASPARCIV_PLUS	0x19
 
 #define IMPL_SPARC64V		0x5
 
+#ifndef __ASM__
+
+#include <arch/types.h>
+#include <typedefs.h>
+#include <arch/register.h>
+#include <arch/regdef.h>
+#include <arch/asm.h>
+
+#ifdef CONFIG_SMP
+#include <arch/mm/cache.h>
+#endif
+
 typedef struct {
 	uint32_t mid;			/**< Processor ID as read from
-					     UPA_CONFIG. */
+					     UPA_CONFIG/FIREPLANE_CONFIG. */
 	ver_reg_t ver;
 	uint32_t clock_frequency;	/**< Processor frequency in Hz. */
@@ -67,5 +73,25 @@
 					     matches this value. */
 } cpu_arch_t;
-	
+
+
+/**
+ * Reads the module ID (agent ID/CPUID) of the current CPU.
+ */
+static inline uint32_t read_mid(void)
+{
+	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
+	icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
+#if defined (US)
+	return icbus_config & 0x1f;
+#elif defined (US3)
+	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
+		return icbus_config & 0x1f;
+	else
+		return icbus_config & 0x3ff;
+#endif
+}
+
+#endif	
+
 #endif
 
Index: kernel/arch/sparc64/include/cpu_family.h
===================================================================
--- kernel/arch/sparc64/include/cpu_family.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
+++ kernel/arch/sparc64/include/cpu_family.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2008 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+
+#ifndef KERN_sparc64_CPU_FAMILY_H_
+#define KERN_sparc64_CPU_FAMILY_H_
+
+#include <arch.h>
+#include <cpu.h>
+#include <arch/register.h>
+#include <arch/asm.h>
+
+/**
+ * Find the processor (sub)family.
+ * 
+ * @return 	true iff the CPU belongs to the US family
+ */
+static inline bool is_us(void)
+{
+	int impl = ((ver_reg_t) ver_read()).impl;
+	return (impl == IMPL_ULTRASPARCI) || (impl == IMPL_ULTRASPARCII) ||
+	       (impl == IMPL_ULTRASPARCII_I) ||  (impl == IMPL_ULTRASPARCII_E);
+}
+
+/**
+ * Find the processor (sub)family.
+ * 
+ * @return 	true iff the CPU belongs to the US-III subfamily
+ */
+static inline bool is_us_iii(void)
+{
+	int impl = ((ver_reg_t) ver_read()).impl;
+	return (impl == IMPL_ULTRASPARCIII) ||
+	       (impl == IMPL_ULTRASPARCIII_PLUS) ||
+	       (impl == IMPL_ULTRASPARCIII_I);
+}
+
+/**
+ * Find the processor (sub)family.
+ * 
+ * @return 	true iff the CPU belongs to the US-IV subfamily
+ */
+static inline bool is_us_iv(void)
+{
+	int impl = ((ver_reg_t) ver_read()).impl;
+	return (impl == IMPL_ULTRASPARCIV) || (impl == IMPL_ULTRASPARCIV_PLUS);
+}
+	
+#endif
+
+/** @}
+ */
Index: kernel/arch/sparc64/include/cpu_node.h
===================================================================
--- kernel/arch/sparc64/include/cpu_node.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
+++ kernel/arch/sparc64/include/cpu_node.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2005 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+
+#ifndef KERN_sparc64_CPU_NODE_H_
+#define KERN_sparc64_CPU_NODE_H_
+
+#include <genarch/ofw/ofw_tree.h>
+
+
+/** Finds the parent node of all the CPU nodes (nodes named "cpu" or "cmp").
+ *
+ *  Depending on the machine type (and possibly the OFW version), CPUs can be
+ *  at "/" or at "/ssm@0,0".
+ */ 
+static inline ofw_tree_node_t *cpus_parent(void)
+{
+	ofw_tree_node_t *parent;
+	parent = ofw_tree_find_child(ofw_tree_lookup("/"), "ssm@0,0");
+	if (parent == NULL)
+		parent = ofw_tree_lookup("/");
+	return parent;
+}
+
+#endif
+
+/** @}
+ */
Index: kernel/arch/sparc64/include/drivers/kbd.h
===================================================================
--- kernel/arch/sparc64/include/drivers/kbd.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/drivers/kbd.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -42,5 +42,6 @@
 	KBD_UNKNOWN,
 	KBD_Z8530,
-	KBD_NS16550
+	KBD_NS16550,
+	KBD_SGCN
 } kbd_type_t;
 
Index: kernel/arch/sparc64/include/drivers/scr.h
===================================================================
--- kernel/arch/sparc64/include/drivers/scr.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/drivers/scr.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -43,5 +43,6 @@
 	SCR_ATYFB,
 	SCR_FFB,
-	SCR_CGSIX
+	SCR_CGSIX,
+	SCR_XVR
 } scr_type_t;
 
Index: kernel/arch/sparc64/include/drivers/sgcn.h
===================================================================
--- kernel/arch/sparc64/include/drivers/sgcn.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
+++ kernel/arch/sparc64/include/drivers/sgcn.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2008 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup sparc64	
+ * @{
+ */
+/** @file
+ */
+
+#ifndef KERN_sparc64_SGCN_H_
+#define KERN_sparc64_SGCN_H_
+
+#include <arch/types.h>
+
+/* number of bytes in the TOC magic, including the terminating '\0' */
+#define TOC_MAGIC_BYTES		8
+
+/* number of bytes in the TOC key, including the terminating '\0' */
+#define TOC_KEY_SIZE		8
+
+/* maximum number of entries in the SRAM table of contents */
+#define MAX_TOC_ENTRIES		32
+
+/* number of bytes in the SGCN buffer magic, including the terminating '\0' */
+#define SGCN_MAGIC_BYTES	4
+
+/**
+ * Entry in the SRAM table of contents. Describes one segment of the SRAM
+ * which serves a particular purpose (e.g. OBP serial console, Solaris serial
+ * console, Solaris mailbox,...). 
+ */
+typedef struct {
+	/** key (e.g. "OBPCONS", "SOLCONS", "SOLMBOX",...) */
+	char key[TOC_KEY_SIZE];
+	
+	/** size of the segment in bytes */
+	uint32_t size;
+	
+	/** offset of the segment within SRAM */
+	uint32_t offset;
+} __attribute ((packed)) toc_entry_t;
+
+/**
+ * SRAM table of contents. Describes all segments within the SRAM.
+ */
+typedef struct {
+	/** hard-wired to "TOCSRAM" */
+	char magic[TOC_MAGIC_BYTES];
+	
+	/** we don't need this */
+	char unused[8];
+	
+	/** TOC entries */
+	toc_entry_t keys[MAX_TOC_ENTRIES];
+} __attribute__ ((packed)) iosram_toc_t;
+
+/**
+ * SGCN buffer header. It is placed at the very beginning of the SGCN
+ * buffer. 
+ */
+typedef struct {
+	/** hard-wired to "CON" */
+	char magic[SGCN_MAGIC_BYTES];
+	
+	/** we don't need this */
+	char unused[8];
+	
+	/** offset within the SGCN buffer of the input buffer start */
+	uint32_t in_begin;
+	
+	/** offset within the SGCN buffer of the input buffer end */
+	uint32_t in_end;
+	
+	/** offset within the SGCN buffer of the input buffer read pointer */
+	uint32_t in_rdptr;
+	
+	/** offset within the SGCN buffer of the input buffer write pointer */
+	uint32_t in_wrptr;
+
+	/** offset within the SGCN buffer of the output buffer start */
+	uint32_t out_begin;
+	
+	/** offset within the SGCN buffer of the output buffer end */
+	uint32_t out_end;
+	
+	/** offset within the SGCN buffer of the output buffer read pointer */
+	uint32_t out_rdptr;
+	
+	/** offset within the SGCN buffer of the output buffer write pointer */
+	uint32_t out_wrptr;
+} __attribute__ ((packed)) sgcn_buffer_header_t;
+
+void sgcn_grab(void);
+void sgcn_release(void);
+void sgcn_poll(void);
+void sgcn_init(void);
+
+#endif
+
+/** @}
+ */
Index: kernel/arch/sparc64/include/mm/cache.h
===================================================================
--- kernel/arch/sparc64/include/mm/cache.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/cache.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -39,13 +39,4 @@
 #include <mm/frame.h>
 
-#define dcache_flush_page(p) \
-	dcache_flush_color(PAGE_COLOR((p)))
-#define dcache_flush_frame(p, f) \
-	dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f)));
-
-extern void dcache_flush(void);
-extern void dcache_flush_color(int c);
-extern void dcache_flush_tag(int c, pfn_t tag);
-
 #endif
 
Index: kernel/arch/sparc64/include/mm/cache_spec.h
===================================================================
--- kernel/arch/sparc64/include/mm/cache_spec.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/cache_spec.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -39,16 +39,17 @@
  * The following macros are valid for the following processors:
  *
- * 	UltraSPARC, UltraSPARC II, UltraSPARC IIi
+ * 	UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
+ * 	UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
  * 
  * Should we support other UltraSPARC processors, we need to make sure that
  * the macros are defined correctly for them.
  */
-
+ 
+#if defined (US)
 #define DCACHE_SIZE		(16 * 1024)
+#elif defined (US3)
+#define DCACHE_SIZE		(64 * 1024)
+#endif
 #define DCACHE_LINE_SIZE	32	
-
-#define ICACHE_SIZE		(16 * 1024)
-#define ICACHE_WAYS		2
-#define ICACHE_LINE_SIZE	32
 
 #endif
Index: kernel/arch/sparc64/include/mm/frame.h
===================================================================
--- kernel/arch/sparc64/include/mm/frame.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/frame.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -60,6 +60,11 @@
 	uintptr_t address;
 	struct {
+#if defined (US)
 		unsigned : 23;
 		uint64_t pfn : 28;		/**< Physical Frame Number. */
+#elif defined (US3)
+		unsigned : 21;
+		uint64_t pfn : 30;		/**< Physical Frame Number. */
+#endif
 		unsigned offset : 13;		/**< Offset. */
 	} __attribute__ ((packed));
Index: kernel/arch/sparc64/include/mm/mmu.h
===================================================================
--- kernel/arch/sparc64/include/mm/mmu.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/mmu.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -36,6 +36,8 @@
 #define KERN_sparc64_MMU_H_
 
+#if defined(US)
 /* LSU Control Register ASI. */
 #define ASI_LSU_CONTROL_REG		0x45	/**< Load/Store Unit Control Register. */
+#endif
 
 /* I-MMU ASIs. */
@@ -53,4 +55,9 @@
 #define VA_IMMU_TSB_BASE		0x28	/**< IMMU TSB base register. */
 #define VA_IMMU_TAG_ACCESS		0x30	/**< IMMU TLB tag access register. */
+#if defined (US3)
+#define VA_IMMU_PRIMARY_EXTENSION	0x48	/**< IMMU TSB primary extension register */
+#define VA_IMMU_NUCLEUS_EXTENSION	0x58	/**< IMMU TSB nucleus extension register */
+#endif
+
 
 /* D-MMU ASIs. */
@@ -74,4 +81,9 @@
 #define VA_DMMU_VA_WATCHPOINT_REG	0x38	/**< DMMU VA data watchpoint register. */
 #define VA_DMMU_PA_WATCHPOINT_REG	0x40	/**< DMMU PA data watchpoint register. */
+#if defined (US3)
+#define VA_DMMU_PRIMARY_EXTENSION	0x48	/**< DMMU TSB primary extension register */
+#define VA_DMMU_SECONDARY_EXTENSION	0x50	/**< DMMU TSB secondary extension register */
+#define VA_DMMU_NUCLEUS_EXTENSION	0x58	/**< DMMU TSB nucleus extension register */
+#endif
 
 #ifndef __ASM__
@@ -81,4 +93,5 @@
 #include <arch/types.h>
 
+#if defined(US)
 /** LSU Control Register. */
 typedef union {
@@ -101,4 +114,5 @@
 	} __attribute__ ((packed));
 } lsu_cr_reg_t;
+#endif /* US */
 
 #endif /* !def __ASM__ */
Index: kernel/arch/sparc64/include/mm/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/tlb.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/tlb.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -36,6 +36,14 @@
 #define KERN_sparc64_TLB_H_
 
+#if defined (US)
 #define ITLB_ENTRY_COUNT		64
 #define DTLB_ENTRY_COUNT		64
+#define DTLB_MAX_LOCKED_ENTRIES		DTLB_ENTRY_COUNT
+#endif
+
+/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
+#if defined (US3)
+#define DTLB_MAX_LOCKED_ENTRIES		16
+#endif
 
 #define MEM_CONTEXT_KERNEL		0
@@ -54,4 +62,7 @@
 #define TLB_DEMAP_PAGE		0
 #define TLB_DEMAP_CONTEXT	1
+#if defined (US3)
+#define TLB_DEMAP_ALL		2
+#endif
 
 #define TLB_DEMAP_TYPE_SHIFT	6
@@ -61,4 +72,16 @@
 #define TLB_DEMAP_SECONDARY	1
 #define TLB_DEMAP_NUCLEUS	2
+
+/* There are more TLBs in one MMU in US3, their codes are defined here. */
+#if defined (US3)
+/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
+#define TLB_DSMALL	0
+#define TLB_DBIG_0	2
+#define TLB_DBIG_1	3
+	
+/* I-MMU: one small (16-entry) TLB and one big TLB */
+#define TLB_ISMALL	0
+#define TLB_IBIG	2
+#endif
 
 #define TLB_DEMAP_CONTEXT_SHIFT	4
@@ -77,4 +100,6 @@
 #include <arch/barrier.h>
 #include <arch/types.h>
+#include <arch/register.h>
+#include <arch/cpu.h>
 
 union tlb_context_reg {
@@ -91,4 +116,7 @@
 
 /** I-/D-TLB Data Access Address in Alternate Space. */
+
+#if defined (US)
+
 union tlb_data_access_addr {
 	uint64_t value;
@@ -99,6 +127,51 @@
 	} __attribute__ ((packed));
 };
-typedef union tlb_data_access_addr tlb_data_access_addr_t;
-typedef union tlb_data_access_addr tlb_tag_read_addr_t;
+typedef union tlb_data_access_addr dtlb_data_access_addr_t;
+typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
+typedef union tlb_data_access_addr itlb_data_access_addr_t;
+typedef union tlb_data_access_addr itlb_tag_read_addr_t;
+
+#elif defined (US3)
+
+/*
+ * In US3, I-MMU and D-MMU have different formats of the data
+ * access register virtual address. In the corresponding
+ * structures the member variable for the entry number is
+ * called "local_tlb_entry" - it contrasts with the "tlb_entry"
+ * for the US data access register VA structure. The rationale
+ * behind this is to prevent careless mistakes in the code
+ * caused by setting only the entry number and not the TLB
+ * number in the US3 code (when taking the code from US). 
+ */
+
+union dtlb_data_access_addr {
+	uint64_t value;
+	struct {
+		uint64_t : 45;
+		unsigned : 1;
+		unsigned tlb_number : 2;
+		unsigned : 4;
+		unsigned local_tlb_entry : 9;
+		unsigned : 3;
+	} __attribute__ ((packed));
+};
+typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
+typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
+
+union itlb_data_access_addr {
+	uint64_t value;
+	struct {
+		uint64_t : 45;
+		unsigned : 1;
+		unsigned tlb_number : 2;
+		unsigned : 6;
+		unsigned local_tlb_entry : 7;
+		unsigned : 3;
+	} __attribute__ ((packed));
+};
+typedef union itlb_data_access_addr itlb_data_access_addr_t;
+typedef union itlb_data_access_addr itlb_tag_read_addr_t;
+
+#endif
 
 /** I-/D-TLB Tag Read Register. */
@@ -119,6 +192,11 @@
 	struct {
 		uint64_t vpn: 51;	/**< Virtual Address bits 63:13. */
+#if defined (US)
 		unsigned : 6;		/**< Ignored. */
 		unsigned type : 1;	/**< The type of demap operation. */
+#elif defined (US3)
+		unsigned : 5;		/**< Ignored. */
+		unsigned type: 2;	/**< The type of demap operation. */
+#endif
 		unsigned context : 2;	/**< Context register selection. */
 		unsigned : 4;		/**< Zero. */
@@ -131,8 +209,17 @@
 	uint64_t value;
 	struct {
+#if defined (US)
 		unsigned long : 40;	/**< Implementation dependent. */
 		unsigned asi : 8;	/**< ASI. */
 		unsigned : 2;
 		unsigned ft : 7;	/**< Fault type. */
+#elif defined (US3)
+		unsigned long : 39;	/**< Implementation dependent. */
+		unsigned nf : 1;	/**< Non-faulting load. */
+		unsigned asi : 8;	/**< ASI. */
+		unsigned tm : 1;	/**< I-TLB miss. */
+		unsigned : 3;		/**< Reserved. */
+		unsigned ft : 5;	/**< Fault type. */
+#endif
 		unsigned e : 1;		/**< Side-effect bit. */
 		unsigned ct : 2;	/**< Context Register selection. */
@@ -145,7 +232,51 @@
 typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
+#if defined (US3)
+
+/*
+ * Functions for determining the number of entries in TLBs. They either return
+ * a constant value or a value based on the CPU autodetection.
+ */
+
+/**
+ * Determine the number of entries in the DMMU's small TLB. 
+ */
+static inline uint16_t tlb_dsmall_size(void)
+{
+	return 16;
+}
+
+/**
+ * Determine the number of entries in each DMMU's big TLB. 
+ */
+static inline uint16_t tlb_dbig_size(void)
+{
+	return 512;
+}
+
+/**
+ * Determine the number of entries in the IMMU's small TLB. 
+ */
+static inline uint16_t tlb_ismall_size(void)
+{
+	return 16;
+}
+
+/**
+ * Determine the number of entries in the IMMU's big TLB. 
+ */
+static inline uint16_t tlb_ibig_size(void)
+{
+	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
+		return 512;
+	else
+		return 128;
+}
+
+#endif
+
 /** Read MMU Primary Context Register.
  *
- * @return Current value of Primary Context Register.
+ * @return		Current value of Primary Context Register.
  */
 static inline uint64_t mmu_primary_context_read(void)
@@ -156,5 +287,5 @@
 /** Write MMU Primary Context Register.
  *
- * @param v New value of Primary Context Register.
+ * @param v		New value of Primary Context Register.
  */
 static inline void mmu_primary_context_write(uint64_t v)
@@ -166,5 +297,5 @@
 /** Read MMU Secondary Context Register.
  *
- * @return Current value of Secondary Context Register.
+ * @return		Current value of Secondary Context Register.
  */
 static inline uint64_t mmu_secondary_context_read(void)
@@ -175,5 +306,5 @@
 /** Write MMU Primary Context Register.
  *
- * @param v New value of Primary Context Register.
+ * @param v		New value of Primary Context Register.
  */
 static inline void mmu_secondary_context_write(uint64_t v)
@@ -183,13 +314,16 @@
 }
 
+#if defined (US)
+
 /** Read IMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
- *
- * @return Current value of specified IMMU TLB Data Access Register.
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified IMMU TLB Data Access
+ * 			Register.
  */
 static inline uint64_t itlb_data_access_read(index_t entry)
 {
-	tlb_data_access_addr_t reg;
+	itlb_data_access_addr_t reg;
 	
 	reg.value = 0;
@@ -200,10 +334,10 @@
 /** Write IMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
- * @param value Value to be written.
+ * @param entry		TLB Entry index.
+ * @param value		Value to be written.
  */
 static inline void itlb_data_access_write(index_t entry, uint64_t value)
 {
-	tlb_data_access_addr_t reg;
+	itlb_data_access_addr_t reg;
 	
 	reg.value = 0;
@@ -215,11 +349,12 @@
 /** Read DMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
- *
- * @return Current value of specified DMMU TLB Data Access Register.
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified DMMU TLB Data Access
+ * 			Register.
  */
 static inline uint64_t dtlb_data_access_read(index_t entry)
 {
-	tlb_data_access_addr_t reg;
+	dtlb_data_access_addr_t reg;
 	
 	reg.value = 0;
@@ -230,10 +365,10 @@
 /** Write DMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
- * @param value Value to be written.
+ * @param entry		TLB Entry index.
+ * @param value		Value to be written.
  */
 static inline void dtlb_data_access_write(index_t entry, uint64_t value)
 {
-	tlb_data_access_addr_t reg;
+	dtlb_data_access_addr_t reg;
 	
 	reg.value = 0;
@@ -245,11 +380,11 @@
 /** Read IMMU TLB Tag Read Register.
  *
- * @param entry TLB Entry index.
- *
- * @return Current value of specified IMMU TLB Tag Read Register.
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified IMMU TLB Tag Read Register.
  */
 static inline uint64_t itlb_tag_read_read(index_t entry)
 {
-	tlb_tag_read_addr_t tag;
+	itlb_tag_read_addr_t tag;
 
 	tag.value = 0;
@@ -260,11 +395,11 @@
 /** Read DMMU TLB Tag Read Register.
  *
- * @param entry TLB Entry index.
- *
- * @return Current value of specified DMMU TLB Tag Read Register.
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified DMMU TLB Tag Read Register.
  */
 static inline uint64_t dtlb_tag_read_read(index_t entry)
 {
-	tlb_tag_read_addr_t tag;
+	dtlb_tag_read_addr_t tag;
 
 	tag.value = 0;
@@ -273,7 +408,118 @@
 }
 
+#elif defined (US3)
+
+
+/** Read IMMU TLB Data Access Register.
+ *
+ * @param tlb		TLB number (one of TLB_ISMALL or TLB_IBIG)
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified IMMU TLB Data Access
+ * 			Register.
+ */
+static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
+{
+	itlb_data_access_addr_t reg;
+	
+	reg.value = 0;
+	reg.tlb_number = tlb;
+	reg.local_tlb_entry = entry;
+	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
+}
+
+/** Write IMMU TLB Data Access Register.
+ * @param tlb		TLB number (one of TLB_ISMALL or TLB_IBIG)
+ * @param entry		TLB Entry index.
+ * @param value		Value to be written.
+ */
+static inline void itlb_data_access_write(int tlb, index_t entry,
+	uint64_t value)
+{
+	itlb_data_access_addr_t reg;
+	
+	reg.value = 0;
+	reg.tlb_number = tlb;
+	reg.local_tlb_entry = entry;
+	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
+	flush_pipeline();
+}
+
+/** Read DMMU TLB Data Access Register.
+ *
+ * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) 
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified DMMU TLB Data Access
+ * 			Register.
+ */
+static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
+{
+	dtlb_data_access_addr_t reg;
+	
+	reg.value = 0;
+	reg.tlb_number = tlb;
+	reg.local_tlb_entry = entry;
+	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
+}
+
+/** Write DMMU TLB Data Access Register.
+ *
+ * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
+ * @param entry		TLB Entry index.
+ * @param value		Value to be written.
+ */
+static inline void dtlb_data_access_write(int tlb, index_t entry,
+	uint64_t value)
+{
+	dtlb_data_access_addr_t reg;
+	
+	reg.value = 0;
+	reg.tlb_number = tlb;
+	reg.local_tlb_entry = entry;
+	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
+	membar();
+}
+
+/** Read IMMU TLB Tag Read Register.
+ *
+ * @param tlb		TLB number (one of TLB_ISMALL or TLB_IBIG) 
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified IMMU TLB Tag Read Register.
+ */
+static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
+{
+	itlb_tag_read_addr_t tag;
+
+	tag.value = 0;
+	tag.tlb_number = tlb;
+	tag.local_tlb_entry = entry;
+	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
+}
+
+/** Read DMMU TLB Tag Read Register.
+ *
+ * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
+ * @param entry		TLB Entry index.
+ *
+ * @return		Current value of specified DMMU TLB Tag Read Register.
+ */
+static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
+{
+	dtlb_tag_read_addr_t tag;
+
+	tag.value = 0;
+	tag.tlb_number = tlb;
+	tag.local_tlb_entry = entry;
+	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
+}
+
+#endif
+
+
 /** Write IMMU TLB Tag Access Register.
  *
- * @param v Value to be written.
+ * @param v		Value to be written.
  */
 static inline void itlb_tag_access_write(uint64_t v)
@@ -285,5 +531,5 @@
 /** Read IMMU TLB Tag Access Register.
  *
- * @return Current value of IMMU TLB Tag Access Register.
+ * @return		Current value of IMMU TLB Tag Access Register.
  */
 static inline uint64_t itlb_tag_access_read(void)
@@ -294,5 +540,5 @@
 /** Write DMMU TLB Tag Access Register.
  *
- * @param v Value to be written.
+ * @param v		Value to be written.
  */
 static inline void dtlb_tag_access_write(uint64_t v)
@@ -304,5 +550,5 @@
 /** Read DMMU TLB Tag Access Register.
  *
- * @return Current value of DMMU TLB Tag Access Register.
+ * @return 		Current value of DMMU TLB Tag Access Register.
  */
 static inline uint64_t dtlb_tag_access_read(void)
@@ -314,5 +560,5 @@
 /** Write IMMU TLB Data in Register.
  *
- * @param v Value to be written.
+ * @param v		Value to be written.
  */
 static inline void itlb_data_in_write(uint64_t v)
@@ -324,5 +570,5 @@
 /** Write DMMU TLB Data in Register.
  *
- * @param v Value to be written.
+ * @param v		Value to be written.
  */
 static inline void dtlb_data_in_write(uint64_t v)
@@ -334,5 +580,5 @@
 /** Read ITLB Synchronous Fault Status Register.
  *
- * @return Current content of I-SFSR register.
+ * @return		Current content of I-SFSR register.
  */
 static inline uint64_t itlb_sfsr_read(void)
@@ -343,5 +589,5 @@
 /** Write ITLB Synchronous Fault Status Register.
  *
- * @param v New value of I-SFSR register.
+ * @param v		New value of I-SFSR register.
  */
 static inline void itlb_sfsr_write(uint64_t v)
@@ -353,5 +599,5 @@
 /** Read DTLB Synchronous Fault Status Register.
  *
- * @return Current content of D-SFSR register.
+ * @return		Current content of D-SFSR register.
  */
 static inline uint64_t dtlb_sfsr_read(void)
@@ -362,5 +608,5 @@
 /** Write DTLB Synchronous Fault Status Register.
  *
- * @param v New value of D-SFSR register.
+ * @param v		New value of D-SFSR register.
  */
 static inline void dtlb_sfsr_write(uint64_t v)
@@ -372,5 +618,5 @@
 /** Read DTLB Synchronous Fault Address Register.
  *
- * @return Current content of D-SFAR register.
+ * @return		Current content of D-SFAR register.
  */
 static inline uint64_t dtlb_sfar_read(void)
@@ -381,8 +627,9 @@
 /** Perform IMMU TLB Demap Operation.
  *
- * @param type Selects between context and page demap.
+ * @param type		Selects between context and page demap (and entire MMU
+ * 			demap on US3).
  * @param context_encoding Specifies which Context register has Context ID for
- * 	demap.
- * @param page Address which is on the page to be demapped.
+ * 			demap.
+ * @param page		Address which is on the page to be demapped.
  */
 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
@@ -398,7 +645,7 @@
 	da.vpn = pg.vpn;
 	
-	asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);	/* da.value is the
-							 * address within the
-							 * ASI */ 
+	/* da.value is the address within the ASI */ 
+	asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
+
 	flush_pipeline();
 }
@@ -406,8 +653,9 @@
 /** Perform DMMU TLB Demap Operation.
  *
- * @param type Selects between context and page demap.
+ * @param type		Selects between context and page demap (and entire MMU
+ * 			demap on US3).
  * @param context_encoding Specifies which Context register has Context ID for
- *	 demap.
- * @param page Address which is on the page to be demapped.
+ * 			demap.
+ * @param page		Address which is on the page to be demapped.
  */
 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
@@ -423,15 +671,15 @@
 	da.vpn = pg.vpn;
 	
-	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);	/* da.value is the
-							 * address within the
-							 * ASI */ 
+	/* da.value is the address within the ASI */ 
+	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
+
 	membar();
 }
 
-extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
-extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
-extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
-
-extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
+extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
+extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
+extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
+
+extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
 extern void dump_sfsr_and_sfar(void);
Index: kernel/arch/sparc64/include/mm/tsb.h
===================================================================
--- kernel/arch/sparc64/include/mm/tsb.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/tsb.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -108,4 +108,53 @@
 }
 
+#if defined (US3)
+
+/** Write DTSB Primary Extension register.
+ *
+ * @param v New content of the DTSB Primary Extension register.
+ */
+static inline void dtsb_primary_extension_write(uint64_t v)
+{
+	asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
+}
+
+/** Write DTSB Secondary Extension register.
+ *
+ * @param v New content of the DTSB Secondary Extension register.
+ */
+static inline void dtsb_secondary_extension_write(uint64_t v)
+{
+	asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
+}
+
+/** Write DTSB Nucleus Extension register.
+ *
+ * @param v New content of the DTSB Nucleus Extension register.
+ */
+static inline void dtsb_nucleus_extension_write(uint64_t v)
+{
+	asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
+}
+
+/** Write ITSB Primary Extension register.
+ *
+ * @param v New content of the ITSB Primary Extension register.
+ */
+static inline void itsb_primary_extension_write(uint64_t v)
+{
+	asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
+}
+
+/** Write ITSB Nucleus Extension register.
+ *
+ * @param v New content of the ITSB Nucleus Extension register.
+ */
+static inline void itsb_nucleus_extension_write(uint64_t v)
+{
+	asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
+}
+
+#endif
+
 /* Forward declarations. */
 struct as;
Index: kernel/arch/sparc64/include/mm/tte.h
===================================================================
--- kernel/arch/sparc64/include/mm/tte.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/mm/tte.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -51,4 +51,5 @@
 #include <arch/types.h>
 
+/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */
 #define VA_TAG_PAGE_SHIFT	22
 
@@ -76,6 +77,11 @@
 		unsigned ie : 1;	/**< Invert Endianness. */
 		unsigned soft2 : 9;	/**< Software defined field. */
+#if defined (US)
 		unsigned diag : 9;	/**< Diagnostic data. */
 		unsigned pfn : 28;	/**< Physical Address bits, bits 40:13. */
+#elif defined (US3)
+		unsigned : 7;		/**< Reserved. */
+		unsigned pfn : 30;	/**< Physical Address bits, bits 42:13 */
+#endif
 		unsigned soft : 6;	/**< Software defined field. */
 		unsigned l : 1;		/**< Lock. */
Index: kernel/arch/sparc64/include/regdef.h
===================================================================
--- kernel/arch/sparc64/include/regdef.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/regdef.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -56,6 +56,9 @@
 #define WSTATE_OTHER(n)		((n) << 3)
 
-#define UPA_CONFIG_MID_SHIFT    17
-#define UPA_CONFIG_MID_MASK     0x1f
+/*
+ * The following definitions concern the UPA_CONFIG register on US and the
+ * FIREPLANE_CONFIG register on US3. 
+ */
+#define ICBUS_CONFIG_MID_SHIFT    17
 
 #endif
Index: kernel/arch/sparc64/include/register.h
===================================================================
--- kernel/arch/sparc64/include/register.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/register.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -118,21 +118,4 @@
 typedef union fprs_reg fprs_reg_t;
 
-/** UPA_CONFIG register.
- *
- * Note that format of this register differs significantly from
- * processor version to version. The format defined here
- * is the common subset for all supported processor versions.
- */
-union upa_config {
-	uint64_t value;
-	struct {
-		uint64_t : 34;
-		unsigned pcon : 8;	/**< Processor configuration. */
-		unsigned mid : 5;	/**< Module (processor) ID register. */
-		unsigned pcap : 17;	/**< Processor capabilities. */
-	} __attribute__ ((packed));
-};
-typedef union upa_config upa_config_t;
-
 #endif
 
Index: kernel/arch/sparc64/include/trap/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/trap/interrupt.h	(revision 8d2760fe0365099552ec91e6cee8c5bbd55ed273)
+++ kernel/arch/sparc64/include/trap/interrupt.h	(revision 965dc18d04fb8a15431d34485959f4aa8e6ec4b5)
@@ -50,19 +50,41 @@
 
 /* Interrupt ASI registers. */
-#define ASI_UDB_INTR_W			0x77
+#define ASI_INTR_W			0x77
 #define ASI_INTR_DISPATCH_STATUS	0x48
-#define ASI_UDB_INTR_R			0x7f
+#define ASI_INTR_R			0x7f
 #define ASI_INTR_RECEIVE		0x49
 
-/* VA's used with ASI_UDB_INTR_W register. */
+/* VA's used with ASI_INTR_W register. */
+#if defined (US)
 #define ASI_UDB_INTR_W_DATA_0	0x40
 #define ASI_UDB_INTR_W_DATA_1	0x50
 #define ASI_UDB_INTR_W_DATA_2	0x60
-#define ASI_UDB_INTR_W_DISPATCH	0x70
+#elif defined (US3)
+#define VA_INTR_W_DATA_0	0x40
+#define VA_INTR_W_DATA_1	0x48
+#define VA_INTR_W_DATA_2	0x50
+#define VA_INTR_W_DATA_3	0x58
+#define VA_INTR_W_DATA_4	0x60
+#define VA_INTR_W_DATA_5	0x68
+#define VA_INTR_W_DATA_6	0x80
+#define VA_INTR_W_DATA_7	0x88
+#endif
+#define VA_INTR_W_DISPATCH	0x70
 
-/* VA's used with ASI_UDB_INTR_R register. */
+/* VA's used with ASI_INTR_R register. */
+#if defined(US)
 #define ASI_UDB_INTR_R_DATA_0	0x40
 #define ASI_UDB_INTR_R_DATA_1	0x50
 #define ASI_UDB_INTR_R_DATA_2	0x60
+#elif defined (US3)
+#define VA_INTR_R_DATA_0	0x40
+#define VA_INTR_R_DATA_1	0x48
+#define VA_INTR_R_DATA_2	0x50
+#define VA_INTR_R_DATA_3	0x58
+#define VA_INTR_R_DATA_4	0x60
+#define VA_INTR_R_DATA_5	0x68
+#define VA_INTR_R_DATA_6	0x80
+#define VA_INTR_R_DATA_7	0x88
+#endif
 
 /* Shifts in the Interrupt Vector Dispatch virtual address. */