Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision 1a2a6e7fe539dc0c3c10afeaf20a054d6132d99a)
+++ boot/arch/arm32/src/mm.c	(revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c)
@@ -143,5 +143,5 @@
 	pte->should_be_zero_1 = 0;
 	pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
-#ifdef PROCESSOR_ARCH_armv7_a
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 	/*
 	 * Keeps this setting in sync with memory type attributes in:
@@ -152,7 +152,7 @@
 	pte->tex = section_cacheable(frame) ? 5 : 0;
 	pte->cacheable = section_cacheable(frame) ? 0 : 0;
-	pte->bufferable = section_cacheable(frame) ? 1 : 0;
+	pte->bufferable = section_cacheable(frame) ? 1 : 1;
 #else
-	pte->bufferable = 1;
+	pte->bufferable = section_cacheable(frame);
 	pte->cacheable = section_cacheable(frame);
 	pte->tex = 0;
Index: kernel/arch/arm32/include/arch/cache.h
===================================================================
--- kernel/arch/arm32/include/arch/cache.h	(revision 1a2a6e7fe539dc0c3c10afeaf20a054d6132d99a)
+++ kernel/arch/arm32/include/arch/cache.h	(revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c)
@@ -46,4 +46,5 @@
 void cpu_dcache_flush_invalidate(void);
 extern void icache_invalidate(void);
+extern void dcache_invalidate(void);
 extern void dcache_clean_mva_pou(uintptr_t);
 
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 1a2a6e7fe539dc0c3c10afeaf20a054d6132d99a)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c)
@@ -257,6 +257,8 @@
 	if (flags & PAGE_CACHEABLE) {
 		/*
-		 * Write-through, write-allocate memory, see ch. B3.8.2
-		 * (p. B3-1358) of ARM Architecture reference manual.
+		 * Outer and inner write-back, write-allocate memory,
+		 * see ch. B3.8.2 (p. B3-1358) of ARM Architecture reference
+		 * manual.
+		 *
 		 * Make sure the memory type is correct, and in sync with:
 		 * init_boot_pt (boot/arch/arm32/src/mm.c)
@@ -277,12 +279,7 @@
 	}
 	
-#if defined(PROCESSOR_ARCH_armv6)
-	/* FIXME: this disables caches */
-	p->shareable = 1;
-#else
 	/* Shareable is ignored for devices (non-cacheable),
 	 * turn it off for normal memory. */
 	p->shareable = 0;
-#endif
 	
 	p->non_global = !(flags & PAGE_GLOBAL);
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 1a2a6e7fe539dc0c3c10afeaf20a054d6132d99a)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c)
@@ -130,5 +130,8 @@
 {
 	uint32_t control_reg = SCTLR_read();
-	
+
+	dcache_invalidate();
+	read_barrier();
+
 	/* Turn off tex remap, RAZ/WI prior to armv7 */
 	control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
@@ -341,4 +344,16 @@
 #endif
 
+void dcache_invalidate(void)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+	dcache_flush_invalidate();
+#else
+	if (cache_is_unified())
+		CIALL_write(0);
+	else
+		DCIALL_write(0);
+#endif
+}
+
 void dcache_clean_mva_pou(uintptr_t mva)
 {