Changes in kernel/arch/arm32/src/cpu/cpu.c [9048147:93d8022] in mainline

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (2 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -130 +130 @@
 {
         uint32_t control_reg = SCTLR_read();
-        
+
+        dcache_invalidate();
+        read_barrier();
+
         /* Turn off tex remap, RAZ/WI prior to armv7 */
         control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
@@ -322 +325 @@
 void icache_invalidate(void)
 {
+#if defined(PROCESSOR_ARCH_armv7_a)
         ICIALLU_write(0);
+#else
+        ICIALL_write(0);
+#endif
+}
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+static bool cache_is_unified(void)
+{
+        if (MIDR_read() != CTR_read()) {
+                /* We have the CTR register */
+                return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
+        } else {
+                panic("Unknown cache type");
+        }
+}
+#endif
+
+void dcache_invalidate(void)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        dcache_flush_invalidate();
+#else
+        if (cache_is_unified())
+                CIALL_write(0);
+        else
+                DCIALL_write(0);
+#endif
+}
+
+void dcache_clean_mva_pou(uintptr_t mva)
+{
+#if defined(PROCESSOR_ARCH_armv7_a)
+        DCCMVAU_write(mva);
+#else
+        if (cache_is_unified())
+                CCMVA_write(mva);
+        else
+                DCCMVA_write(mva);
+#endif
 }