Index: kernel/arch/ppc32/include/barrier.h
===================================================================
--- kernel/arch/ppc32/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
+++ kernel/arch/ppc32/include/barrier.h	(revision 934b2e0be99407bebe9e2a8fbb2ebaf1242b8c46)
@@ -43,6 +43,40 @@
 #define write_barrier() asm volatile ("eieio" ::: "memory")
 
-#define smc_coherence(a)
-#define smc_coherence_block(a, l)
+/*
+ * The IMB sequence used here is valid for all possible cache models
+ * on uniprocessor. SMP might require a different sequence.
+ * See PowerPC Programming Environment for 32-Bit Microprocessors,
+ * chapter 5.1.5.2
+ */
+
+static inline void smc_coherence(void *addr)
+{
+	asm volatile (
+		"dcbst 0, %0\n"
+		"sync\n"
+		"icbi 0, %0\n"
+		"isync\n"
+		:: "r" (addr)
+	);
+}
+
+#define COHERENCE_INVAL_MIN	4
+
+static inline void smc_coherence_block(void *addr, unsigned long len)
+{
+	unsigned long i;
+
+	for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
+		asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
+	}
+
+	asm volatile ("sync");
+
+	for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
+		asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
+	}
+
+	asm volatile ("isync");
+}
 
 #endif