Index: uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h
===================================================================
--- uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -43,4 +43,13 @@
 
 	volatile uint32_t transaction[8];
+	volatile uint32_t buffer_pointer[7];
+
+	/* 64 bit struct only */
+	volatile uint32_t extended_bp[7];
+} __attribute__((packed, aligned(32))) itd_t;
+
+/*
+ * itd_t.transaction
+ */
 #define ITD_TRANSACTION_STATUS_ACTIVE_FLAG  (1 << 31)
 #define ITD_TRANSACTION_STATUS_BUFFER_ERROR_FLAG  (1 << 30)
@@ -55,5 +64,7 @@
 #define ITD_TRANSACTION_OFFSET_SHIFT   0
 
-	volatile uint32_t buffer_pointer[7];
+/*
+ * itd_t.buffer_pointer
+ */
 #define ITD_BUFFER_POINTER_MASK      0xfffff000
 /* First buffer pointer */
@@ -70,8 +81,6 @@
 #define ITD_BUFFER_POINTER_MULTI_SHIFT   0
 
-	/* 64 bit struct only */
-	volatile uint32_t extended_bp[7];
-} __attribute__((packed, aligned(32))) itd_t;
 #endif
+
 /**
  * @}
Index: uspace/drv/bus/usb/ehci/hw_struct/queue_head.h
===================================================================
--- uspace/drv/bus/usb/ehci/hw_struct/queue_head.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/ehci/hw_struct/queue_head.h	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -49,4 +49,20 @@
 
 	volatile uint32_t ep_char;
+	volatile uint32_t ep_cap;
+
+	link_pointer_t current;
+	/* Transfer overlay starts here */
+	link_pointer_t next;
+	link_pointer_t alternate;
+	volatile uint32_t status;
+	volatile uint32_t buffer_pointer[5];
+
+	/* 64 bit struct only */
+	volatile uint32_t extended_bp[5];
+} __attribute__((packed, aligned(32))) qh_t;
+
+/*
+ * qh_t.ep_char
+ */
 #define QH_EP_CHAR_RL_MASK    0xf
 #define QH_EP_CHAR_RL_SHIFT   28
@@ -78,5 +94,7 @@
     (((val) >> QH_EP_CHAR_ADDR_SHIFT) & QH_EP_CHAR_ADDR_MASK)
 
-	volatile uint32_t ep_cap;
+/*
+ * qh_t.ep_cap
+ */
 #define QH_EP_CAP_MULTI_MASK   0x3
 #define QH_EP_CAP_MULTI_SHIFT  30
@@ -100,12 +118,13 @@
 	(((val) & QH_EP_CAP_S_MASK_MASK) << QH_EP_CAP_S_MASK_SHIFT)
 
-	link_pointer_t current;
-/* Transfer overlay starts here */
-	link_pointer_t next;
-	link_pointer_t alternate;
+/*
+ * qh_t.alternate
+ */
 #define QH_ALTERNATE_NACK_CNT_MASK   0x7
 #define QH_ALTERNATE_NACK_CNT_SHIFT  1
 
-	volatile uint32_t status;
+/*
+ * qh_t.status
+ */
 #define QH_STATUS_TOGGLE_FLAG   (1 << 31)
 #define QH_STATUS_TOTAL_MASK    0x7fff
@@ -127,5 +146,7 @@
 #define QH_STATUS_PING_FLAG     (1 << 0)
 
-	volatile uint32_t buffer_pointer[5];
+/*
+ * qh_t.buffer_pointer
+ */
 #define QH_BUFFER_POINTER_MASK   0xfffff000
 /* Only the first buffer pointer */
@@ -141,7 +162,4 @@
 #define QH_BUFFER_POINTER_FTAG_SHIFT  0
 
-	/* 64 bit struct only */
-	volatile uint32_t extended_bp[5];
-} __attribute__((packed, aligned(32))) qh_t;
 
 static inline void qh_append_qh(qh_t *qh, const qh_t *next)
@@ -212,6 +230,6 @@
 }
 
-
-void qh_init(qh_t *instance, const endpoint_t *ep);
+extern void qh_init(qh_t *instance, const endpoint_t *ep);
+
 #endif
 /**
Index: uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h
===================================================================
--- uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -43,4 +43,16 @@
 
 	volatile uint32_t ep;
+	volatile uint32_t uframe;
+	volatile uint32_t status;
+	volatile uint32_t buffer_pointer[2];
+	link_pointer_t back;
+
+	/* 64 bit struct only */
+	volatile uint32_t extended_bp[2];
+} __attribute__((packed, aligned(32))) sitd_t;
+
+/*
+ * sitd_t.ep
+ */
 #define SITD_EP_IN_FLAG         (1 << 31)
 #define SITD_EP_PORT_MASK       0x3f
@@ -53,5 +65,7 @@
 #define SITD_EP_ADDR_SHIFT      0
 
-	volatile uint32_t uframe;
+/*
+ * sitd_t.uframe
+ */
 #define SITD_uFRAME_CMASK_MASK    0xff
 #define SITD_uFRAME_CMASK_SHIFT   8
@@ -59,5 +73,7 @@
 #define SITD_uFRAME_SMASK_SHIFT   0
 
-	volatile uint32_t status;
+/*
+ * sitd_t.status
+ */
 #define SITD_STATUS_IOC_FLAG            (1 << 31)
 #define SITD_STATUS_PAGE_FLAG           (1 << 30)
@@ -74,5 +90,7 @@
 #define SITD_STATUS_SPLIT_COMPLETE_FLAG (1 << 1)
 
-	volatile uint32_t buffer_pointer[2];
+/*
+ * sitd_t.buffer_pointer
+ */
 #define SITD_BUFFER_POINTER_MASK   0xfffff000
 /* Only the first page pointer */
@@ -85,10 +103,6 @@
 #define SITD_BUFFER_POINTER_COUNT_SHIFT   0
 
-	link_pointer_t back;
+#endif
 
-	/* 64 bit struct only */
-	volatile uint32_t extended_bp[2];
-} __attribute__((packed, aligned(32))) sitd_t;
-#endif
 /**
  * @}
Index: uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h
===================================================================
--- uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -47,4 +47,15 @@
 
 	volatile uint32_t status;
+
+	volatile uint32_t buffer_pointer[5];
+
+	/* 64 bit struct only */
+	volatile uint32_t extended_bp[5];
+
+} __attribute__((packed, aligned(32))) td_t;
+
+/*
+ * td_t.status
+ */
 #define TD_STATUS_TOGGLE_FLAG   (1 << 31)
 #define TD_STATUS_TOTAL_MASK    0x7fff
@@ -69,13 +80,11 @@
 #define TD_STATUS_PING_FLAG     (1 << 0)
 
-	volatile uint32_t buffer_pointer[5];
+/*
+ * td_t.buffer_pointer
+ */
+
 #define TD_BUFFER_POINTER_MASK   0xfffff000
 /* Only the first page pointer */
 #define TD_BUFFER_POINTER_OFFSET_MASK    0xfff
-
-	/* 64 bit struct only */
-	volatile uint32_t extended_bp[5];
-
-} __attribute__((packed, aligned(32))) td_t;
 
 static_assert(sizeof(td_t) % 32 == 0);
Index: uspace/drv/bus/usb/ohci/ohci_regs.h
===================================================================
--- uspace/drv/bus/usb/ohci/ohci_regs.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/ohci/ohci_regs.h	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -50,69 +50,20 @@
 typedef struct ohci_regs {
 	const ioport32_t revision;
-#define R_REVISION_MASK (0x3f)
-#define R_LEGACY_FLAG   (0x80)
 
 	ioport32_t control;
-/* Control-bulk service ratio */
-#define C_CBSR_1_1  (0x0)
-#define C_CBSR_1_2  (0x1)
-#define C_CBSR_1_3  (0x2)
-#define C_CBSR_1_4  (0x3)
-#define C_CBSR_MASK (0x3)
-#define C_CBSR_SHIFT 0
-
-#define C_PLE (1 << 2)   /* Periodic list enable */
-#define C_IE  (1 << 3)   /* Isochronous enable */
-#define C_CLE (1 << 4)   /* Control list enable */
-#define C_BLE (1 << 5)   /* Bulk list enable */
-
-/* Host controller functional state */
-#define C_HCFS_RESET       (0x0)
-#define C_HCFS_RESUME      (0x1)
-#define C_HCFS_OPERATIONAL (0x2)
-#define C_HCFS_SUSPEND     (0x3)
-#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
-#define C_HCFS_SET(reg, value) \
-do { \
-	uint32_t r = OHCI_RD(reg); \
-	r &= ~(0x3 << 6); \
-	r |= (value & 0x3) << 6; \
-	OHCI_WR(reg, r); \
-} while (0)
-
-#define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
-#define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
-#define C_RWE (1 << 10)  /* Remote wakeup enable */
 
 	ioport32_t command_status;
-#define CS_HCR (1 << 0)   /* Host controller reset */
-#define CS_CLF (1 << 1)   /* Control list filled */
-#define CS_BLF (1 << 2)   /* Bulk list filled */
-#define CS_OCR (1 << 3)   /* Ownership change request */
-#if 0
-#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
-#define CS_SOC_SHIFT (16)
-#endif
 
 	/** Interupt enable/disable/status,
 	 * reads give the same value,
 	 * writing causes enable/disable,
-	 * status is write-clean (writing 1 clears the bit*/
+	 * status is write-clean (writing 1 clears the bit
+	 */
 	ioport32_t interrupt_status;
 	ioport32_t interrupt_enable;
 	ioport32_t interrupt_disable;
-#define I_SO   (1 << 0)   /* Scheduling overrun */
-#define I_WDH  (1 << 1)   /* Done head write-back */
-#define I_SF   (1 << 2)   /* Start of frame */
-#define I_RD   (1 << 3)   /* Resume detect */
-#define I_UE   (1 << 4)   /* Unrecoverable error */
-#define I_FNO  (1 << 5)   /* Frame number overflow */
-#define I_RHSC (1 << 6)   /* Root hub status change */
-#define I_OC   (1 << 30)  /* Ownership change */
-#define I_MI   (1 << 31)  /* Master interrupt (any/all) */
 
 	/** HCCA pointer (see hw_struct hcca.h) */
 	ioport32_t hcca;
-#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
 
 	/** Currently executed periodic endpoint */
@@ -136,82 +87,25 @@
 	/** Frame time and max packet size for all transfers */
 	ioport32_t fm_interval;
-#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
-#define FMI_FI_SHIFT (0)
-#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
-#define FMI_FSMPS_SHIFT (16)
-#define FMI_TOGGLE_FLAG (1 << 31)
 
 	/** Bit times remaining in current frame */
 	const ioport32_t fm_remaining;
-#define FMR_FR_MASK FMI_FI_MASK
-#define FMR_FR_SHIFT FMI_FI_SHIFT
-#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
 
 	/** Frame number */
 	const ioport32_t fm_number;
-#define FMN_NUMBER_MASK (0xffff)
 
 	/** Remaining bit time in frame to start periodic transfers */
 	ioport32_t periodic_start;
-#define PS_MASK 0x3fff
-#define PS_SHIFT 0
 
 	/** Threshold for starting LS transaction */
 	ioport32_t ls_threshold;
-#define LST_LST_MASK (0x7fff)
 
 	/** The first root hub control register */
 	ioport32_t rh_desc_a;
-/** Number of downstream ports, max 15 */
-#define RHDA_NDS_MASK  (0xff)
-/** Power switching mode: 0-global, 1-per port*/
-#define RHDA_PSM_FLAG  (1 << 8)
-/** No power switch: 1-power on, 0-use PSM*/
-#define RHDA_NPS_FLAG  (1 << 9)
-/** 1-Compound device, must be 0 */
-#define RHDA_DT_FLAG   (1 << 10)
-/** Over-current mode: 0-global, 1-per port */
-#define RHDA_OCPM_FLAG (1 << 11)
-/** OC control: 0-use OCPM, 1-OC off */
-#define RHDA_NOCP_FLAG (1 << 12)
-/** Power on to power good time */
-#define RHDA_POTPGT_SHIFT   24
 
 	/** The other root hub control register */
 	ioport32_t rh_desc_b;
-/** Device removable mask */
-#define RHDB_DR_SHIFT   0
-#define RHDB_DR_MASK    0xffffU
-/** Power control mask */
-#define RHDB_PCC_MASK	0xffffU
-#define RHDB_PCC_SHIFT	16
 
 	/** Root hub status register */
 	ioport32_t rh_status;
-/* read: 0,
- * write: 0-no effect,
- *        1-turn off port power for ports
- *        specified in PPCM(RHDB), or all ports,
- *        if power is set globally */
-#define RHS_LPS_FLAG  (1 <<  0)
-#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
-/** Over-current indicator, if per-port: 0 */
-#define RHS_OCI_FLAG  (1 <<  1)
-
-/* read: 0-connect status change does not wake HC
- *       1-connect status change wakes HC
- * write: 1-set DRWE, 0-no effect */
-#define RHS_DRWE_FLAG (1 << 15)
-#define RHS_SET_DRWE RHS_DRWE_FLAG
-/* read: 0,
- * write: 0-no effect
- *        1-turn on port power for ports
- *        specified in PPCM(RHDB), or all ports,
- *        if power is set globally */
-#define RHS_LPSC_FLAG (1 << 16)
-#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
-/** Over-current change indicator*/
-#define RHS_OCIC_FLAG (1 << 17)
-#define RHS_CLEAR_DRWE (1 << 31)
 
 	/** Root hub per port status */
@@ -249,5 +143,223 @@
 } ohci_regs_t;
 
+/*
+ * ohci_regs_t.revision
+ */
+
+#define R_REVISION_MASK (0x3f)
+#define R_LEGACY_FLAG   (0x80)
+
+/*
+ * ohci_regs_t.control
+ */
+ 
+/* Control-bulk service ratio */
+#define C_CBSR_1_1  (0x0)
+#define C_CBSR_1_2  (0x1)
+#define C_CBSR_1_3  (0x2)
+#define C_CBSR_1_4  (0x3)
+#define C_CBSR_MASK (0x3)
+#define C_CBSR_SHIFT 0
+
+#define C_PLE (1 << 2)   /* Periodic list enable */
+#define C_IE  (1 << 3)   /* Isochronous enable */
+#define C_CLE (1 << 4)   /* Control list enable */
+#define C_BLE (1 << 5)   /* Bulk list enable */
+
+/* Host controller functional state */
+#define C_HCFS_RESET       (0x0)
+#define C_HCFS_RESUME      (0x1)
+#define C_HCFS_OPERATIONAL (0x2)
+#define C_HCFS_SUSPEND     (0x3)
+#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
+#define C_HCFS_SET(reg, value) \
+do { \
+	uint32_t r = OHCI_RD(reg); \
+	r &= ~(0x3 << 6); \
+	r |= (value & 0x3) << 6; \
+	OHCI_WR(reg, r); \
+} while (0)
+
+#define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
+#define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
+#define C_RWE (1 << 10)  /* Remote wakeup enable */
+
+/*
+ * ohci_regs_t.command_status
+ */
+
+#define CS_HCR (1 << 0)   /* Host controller reset */
+#define CS_CLF (1 << 1)   /* Control list filled */
+#define CS_BLF (1 << 2)   /* Bulk list filled */
+#define CS_OCR (1 << 3)   /* Ownership change request */
+#if 0
+#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
+#define CS_SOC_SHIFT (16)
 #endif
+
+/*
+ * ohci_regs_t.interrupt_xxx
+ */
+
+#define I_SO   (1 << 0)   /* Scheduling overrun */
+#define I_WDH  (1 << 1)   /* Done head write-back */
+#define I_SF   (1 << 2)   /* Start of frame */
+#define I_RD   (1 << 3)   /* Resume detect */
+#define I_UE   (1 << 4)   /* Unrecoverable error */
+#define I_FNO  (1 << 5)   /* Frame number overflow */
+#define I_RHSC (1 << 6)   /* Root hub status change */
+#define I_OC   (1 << 30)  /* Ownership change */
+#define I_MI   (1 << 31)  /* Master interrupt (any/all) */
+
+
+/*
+ * ohci_regs_t.hcca
+ */
+
+#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
+
+/*
+ * ohci_regs_t.fm_interval
+ */
+
+#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
+#define FMI_FI_SHIFT (0)
+#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
+#define FMI_FSMPS_SHIFT (16)
+#define FMI_TOGGLE_FLAG (1 << 31)
+
+/*
+ * ohci_regs_t.fm_remaining
+ */
+
+#define FMR_FR_MASK FMI_FI_MASK
+#define FMR_FR_SHIFT FMI_FI_SHIFT
+#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
+
+/*
+ * ohci_regs_t.fm_number
+ */
+
+#define FMN_NUMBER_MASK (0xffff)
+
+/*
+ * ohci_regs_t.periodic_start
+ */
+
+#define PS_MASK 0x3fff
+#define PS_SHIFT 0
+
+/*
+ * ohci_regs_t.ls_threshold
+ */
+
+#define LST_LST_MASK (0x7fff)
+
+/*
+ * ohci_regs_t.rh_desc_a
+ */
+
+/** Number of downstream ports, max 15 */
+#define RHDA_NDS_MASK  (0xff)
+/** Power switching mode: 0-global, 1-per port*/
+#define RHDA_PSM_FLAG  (1 << 8)
+/** No power switch: 1-power on, 0-use PSM*/
+#define RHDA_NPS_FLAG  (1 << 9)
+/** 1-Compound device, must be 0 */
+#define RHDA_DT_FLAG   (1 << 10)
+/** Over-current mode: 0-global, 1-per port */
+#define RHDA_OCPM_FLAG (1 << 11)
+/** OC control: 0-use OCPM, 1-OC off */
+#define RHDA_NOCP_FLAG (1 << 12)
+/** Power on to power good time */
+#define RHDA_POTPGT_SHIFT   24
+
+/*
+ * ohci_regs_t.rh_desc_b
+ */
+
+/** Device removable mask */
+#define RHDB_DR_SHIFT   0
+#define RHDB_DR_MASK    0xffffU
+
+/** Power control mask */
+#define RHDB_PCC_MASK	0xffffU
+#define RHDB_PCC_SHIFT	16
+
+/*
+ * ohci_regs_t.rh_status
+ */
+
+/*
+ * read: 0,
+ * write: 0-no effect,
+ *        1-turn off port power for ports
+ *        specified in PPCM(RHDB), or all ports,
+ *        if power is set globally
+ */
+#define RHS_LPS_FLAG  (1 <<  0)
+#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
+/** Over-current indicator, if per-port: 0 */
+#define RHS_OCI_FLAG  (1 <<  1)
+/*
+ * read: 0-connect status change does not wake HC
+ *       1-connect status change wakes HC
+ * write: 1-set DRWE, 0-no effect
+ */
+#define RHS_DRWE_FLAG (1 << 15)
+#define RHS_SET_DRWE RHS_DRWE_FLAG
+/*
+ * read: 0,
+ * write: 0-no effect
+ *        1-turn on port power for ports
+ *        specified in PPCM(RHDB), or all ports,
+ *        if power is set globally
+ */
+#define RHS_LPSC_FLAG (1 << 16)
+#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
+/** Over-current change indicator*/
+#define RHS_OCIC_FLAG (1 << 17)
+#define RHS_CLEAR_DRWE (1 << 31)
+
+#endif
+
+/*
+ * ohci_regs_t.rh_port_status[x]
+ */
+
+/** r: current connect status, w: 1-clear port enable, 0-N/S*/
+#define RHPS_CCS_FLAG (1 << 0)
+#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
+/** r: port enable status, w: 1-set port enable, 0-N/S */
+#define RHPS_PES_FLAG (1 << 1)
+#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
+/** r: port suspend status, w: 1-set port suspend, 0-N/S */
+#define RHPS_PSS_FLAG (1 << 2)
+#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
+/** r: port over-current (if reports are per-port
+ * w: 1-clear port suspend (start resume if suspened), 0-nothing
+ */
+#define RHPS_POCI_FLAG (1 << 3)
+#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
+/** r: port reset status, w: 1-set port reset, 0-N/S */
+#define RHPS_PRS_FLAG (1 << 4)
+#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
+/** r: port power status, w: 1-set port power, 0-N/S */
+#define RHPS_PPS_FLAG (1 << 8)
+#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
+/** r: low speed device attached, w: 1-clear port power, 0-N/S */
+#define RHPS_LSDA_FLAG (1 << 9)
+#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
+/** connect status change WC */
+#define RHPS_CSC_FLAG  (1 << 16)
+/** port enable status change WC */
+#define RHPS_PESC_FLAG (1 << 17)
+/** port suspend status change WC */
+#define RHPS_PSSC_FLAG (1 << 18)
+/** port over-current change WC */
+#define RHPS_OCIC_FLAG (1 << 19)
+/** port reset status change WC */
+#define RHPS_PRSC_FLAG (1 << 20)
+#define RHPS_CHANGE_WC_MASK (0x1f0000)
 
 /**
Index: uspace/drv/bus/usb/uhci/hc.c
===================================================================
--- uspace/drv/bus/usb/uhci/hc.c	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/uhci/hc.c	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -531,6 +531,8 @@
 	    &instance->transfers_control_slow);
 
-	/*FSBR, This feature is not needed (adds no benefit) and is supposedly
-	 * buggy on certain hw, enable at your own risk. */
+	/*
+	 * FSBR, This feature is not needed (adds no benefit) and is supposedly
+	 * buggy on certain hw, enable at your own risk.
+	 */
 #ifdef FSBR
 	transfer_list_set_next(&instance->transfers_bulk_full,
Index: uspace/drv/bus/usb/xhci/commands.h
===================================================================
--- uspace/drv/bus/usb/xhci/commands.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ uspace/drv/bus/usb/xhci/commands.h	(revision 904b1bc3e43b98f81bec9e9296b154371c383776)
@@ -79,12 +79,15 @@
 	xhci_trb_ring_t trb_ring;
 
-	fibril_mutex_t guard;		/**< Guard access to this structure. */
+	/** Guard access to this structure. */
+	fibril_mutex_t guard;
 	list_t cmd_list;
 
-	xhci_cr_state_t state;		/**< Whether commands are allowed to be
-					     added. */
-	fibril_condvar_t state_cv;	/**< For waiting on CR state change. */
+	/** Whether commands are allowed to be added. */
+	xhci_cr_state_t state;
+	/** For waiting on CR state change. */
+	fibril_condvar_t state_cv;
 
-	fibril_condvar_t stopped_cv;	/**< For waiting on CR stopped event. */
+	/** For waiting on CR stopped event. */
+	fibril_condvar_t stopped_cv;
 } xhci_cmd_ring_t;
 
@@ -108,5 +111,6 @@
 
 	/** Below are arguments of all commands mixed together.
-	 *  Be sure to know which command accepts what arguments. */
+	 *  Be sure to know which command accepts what arguments.
+	 */
 
 	uint32_t slot_id;