Index: kernel/arch/amd64/src/boot/memmap.c =================================================================== --- kernel/arch/amd64/src/boot/memmap.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/boot/memmap.c (revision 8fb1bf822f6a9bc8f1cfcf6d4f55e602effe5401) @@ -35,5 +35,5 @@ #include -uint8_t e820counter = 0xff; +uint8_t e820counter = 0xffU; e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS]; Index: kernel/arch/amd64/src/cpu/cpu.c =================================================================== --- kernel/arch/amd64/src/cpu/cpu.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/cpu/cpu.c (revision 8fb1bf822f6a9bc8f1cfcf6d4f55e602effe5401) @@ -47,12 +47,11 @@ * Contains only non-MP-Specification specific SMP code. */ -#define AMD_CPUID_EBX 0x68747541 -#define AMD_CPUID_ECX 0x444d4163 -#define AMD_CPUID_EDX 0x69746e65 +#define AMD_CPUID_EBX UINT32_C(0x68747541) +#define AMD_CPUID_ECX UINT32_C(0x444d4163) +#define AMD_CPUID_EDX UINT32_C(0x69746e65) -#define INTEL_CPUID_EBX 0x756e6547 -#define INTEL_CPUID_ECX 0x6c65746e -#define INTEL_CPUID_EDX 0x49656e69 - +#define INTEL_CPUID_EBX UINT32_C(0x756e6547) +#define INTEL_CPUID_ECX UINT32_C(0x6c65746e) +#define INTEL_CPUID_EDX UINT32_C(0x49656e69) enum vendor { Index: kernel/arch/amd64/src/debugger.c =================================================================== --- kernel/arch/amd64/src/debugger.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/debugger.c (revision 8fb1bf822f6a9bc8f1cfcf6d4f55e602effe5401) @@ -126,5 +126,5 @@ /* Disable breakpoint in DR7 */ unative_t dr7 = read_dr7(); - dr7 &= ~(0x2 << (curidx * 2)); + dr7 &= ~(0x02U << (curidx * 2)); /* Setup DR register */ @@ -147,24 +147,24 @@ /* Set type to requested breakpoint & length*/ - dr7 &= ~(0x3 << (16 + 4 * curidx)); - dr7 &= ~(0x3 << (18 + 4 * curidx)); + dr7 &= ~(0x03U << (16 + 4 * curidx)); + dr7 &= ~(0x03U << (18 + 4 * curidx)); if (!(flags & BKPOINT_INSTR)) { #ifdef __32_BITS__ - dr7 |= ((unative_t) 0x3) << (18 + 4 * curidx); + dr7 |= ((unative_t) 0x03U) << (18 + 4 * curidx); #endif #ifdef __64_BITS__ - dr7 |= ((unative_t) 0x2) << (18 + 4 * curidx); + dr7 |= ((unative_t) 0x02U) << (18 + 4 * curidx); #endif if ((flags & BKPOINT_WRITE)) - dr7 |= ((unative_t) 0x1) << (16 + 4 * curidx); + dr7 |= ((unative_t) 0x01U) << (16 + 4 * curidx); else if ((flags & BKPOINT_READ_WRITE)) - dr7 |= ((unative_t) 0x3) << (16 + 4 * curidx); + dr7 |= ((unative_t) 0x03U) << (16 + 4 * curidx); } /* Enable global breakpoint */ - dr7 |= 0x2 << (curidx * 2); + dr7 |= 0x02U << (curidx * 2); write_dr7(dr7); Index: kernel/arch/amd64/src/pm.c =================================================================== --- kernel/arch/amd64/src/pm.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/pm.c (revision 8fb1bf822f6a9bc8f1cfcf6d4f55e602effe5401) @@ -28,5 +28,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -52,57 +52,57 @@ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* KTEXT descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 1, .special = 0, - .granularity = 1, + .granularity = 1, .base_24_31 = 0 }, /* KDATA descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 0, - .special = 0, - .granularity = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 0, + .special = 0, + .granularity = 1, .base_24_31 = 0 }, /* UDATA descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 0, - .special = 1, - .granularity = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 0, + .special = 1, + .granularity = 1, .base_24_31 = 0 }, /* UTEXT descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_CODE | DPL_USER, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 1, - .special = 0, - .granularity = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_CODE | DPL_USER, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 1, + .special = 0, + .granularity = 1, .base_24_31 = 0 }, /* KTEXT 32-bit protected, for protected mode before long mode */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 0, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 0, .special = 1, - .granularity = 1, + .granularity = 1, .base_24_31 = 0 }, /* TSS descriptor - set up will be completed later, @@ -111,7 +111,8 @@ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* VESA Init descriptor */ -#ifdef CONFIG_FB - { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, - 0xf, 0, 0, 0, 0, 0 +#ifdef CONFIG_FB + { + 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, + 0xf, 0, 0, 0, 0, 0 } #endif @@ -129,8 +130,8 @@ { tss_descriptor_t *td = (tss_descriptor_t *) d; - - td->base_0_15 = base & 0xffff; - td->base_16_23 = ((base) >> 16) & 0xff; - td->base_24_31 = ((base) >> 24) & 0xff; + + td->base_0_15 = base & 0xffffU; + td->base_16_23 = ((base) >> 16) & 0xffU; + td->base_24_31 = ((base) >> 24) & 0xffU; td->base_32_63 = ((base) >> 32); } @@ -140,6 +141,6 @@ tss_descriptor_t *td = (tss_descriptor_t *) d; - td->limit_0_15 = limit & 0xffff; - td->limit_16_19 = (limit >> 16) & 0xf; + td->limit_0_15 = limit & 0xffffU; + td->limit_16_19 = (limit >> 16) & 0x0fU; } @@ -149,6 +150,6 @@ * Offset is a linear address. */ - d->offset_0_15 = offset & 0xffff; - d->offset_16_31 = offset >> 16 & 0xffff; + d->offset_0_15 = offset & 0xffffU; + d->offset_16_31 = (offset >> 16) & 0xffffU; d->offset_32_63 = offset >> 32; } @@ -165,16 +166,16 @@ { idescriptor_t *d; - int i; - + unsigned int i; + for (i = 0; i < IDT_ITEMS; i++) { d = &idt[i]; - + d->unused = 0; d->selector = GDT_SELECTOR(KTEXT_DES); - + d->present = 1; - d->type = AR_INTERRUPT; /* masking interrupt */ + d->type = AR_INTERRUPT; /* masking interrupt */ } - + d = &idt[0]; idt_setoffset(d++, (uintptr_t) &int_0);