Index: kernel/arch/sparc64/include/arch/trap/regwin.S =================================================================== --- kernel/arch/sparc64/include/arch/trap/regwin.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) +++ kernel/arch/sparc64/include/arch/trap/regwin.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains register window trap handlers. + */ + +/* + * Macro used by the nucleus and the primary context 0 during normal and other spills. + */ +.macro SPILL_NORMAL_HANDLER_KERNEL + stx %l0, [%sp + STACK_BIAS + L0_OFFSET] + stx %l1, [%sp + STACK_BIAS + L1_OFFSET] + stx %l2, [%sp + STACK_BIAS + L2_OFFSET] + stx %l3, [%sp + STACK_BIAS + L3_OFFSET] + stx %l4, [%sp + STACK_BIAS + L4_OFFSET] + stx %l5, [%sp + STACK_BIAS + L5_OFFSET] + stx %l6, [%sp + STACK_BIAS + L6_OFFSET] + stx %l7, [%sp + STACK_BIAS + L7_OFFSET] + stx %i0, [%sp + STACK_BIAS + I0_OFFSET] + stx %i1, [%sp + STACK_BIAS + I1_OFFSET] + stx %i2, [%sp + STACK_BIAS + I2_OFFSET] + stx %i3, [%sp + STACK_BIAS + I3_OFFSET] + stx %i4, [%sp + STACK_BIAS + I4_OFFSET] + stx %i5, [%sp + STACK_BIAS + I5_OFFSET] + stx %i6, [%sp + STACK_BIAS + I6_OFFSET] + stx %i7, [%sp + STACK_BIAS + I7_OFFSET] + saved + retry +.endm + +/* + * Macro used by the userspace during normal spills. + */ +.macro SPILL_NORMAL_HANDLER_USERSPACE + wr %g0, ASI_AIUP, %asi + stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi + stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi + stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi + stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi + stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi + stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi + stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi + stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi + stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi + stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi + stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi + stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi + stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi + stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi + stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi + stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi + saved + retry +.endm + +/* + * Macro used by the nucleus and the primary context 0 during normal fills. + */ +.macro FILL_NORMAL_HANDLER_KERNEL + ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 + ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 + ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 + ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 + ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 + ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 + ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 + ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 + ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 + ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 + ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 + ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 + ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 + ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 + ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 + ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 + restored + retry +.endm + +/* + * Macro used by the userspace during normal fills. + */ +.macro FILL_NORMAL_HANDLER_USERSPACE + wr %g0, ASI_AIUP, %asi + ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0 + ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1 + ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2 + ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3 + ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4 + ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5 + ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6 + ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7 + ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0 + ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1 + ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2 + ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3 + ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4 + ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5 + ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6 + ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7 + restored + retry +.endm + +.macro CLEAN_WINDOW_HANDLER + rdpr %cleanwin, %l0 + add %l0, 1, %l0 + wrpr %l0, 0, %cleanwin +#if defined(SUN4U) + mov %r0, %l0 + mov %r0, %l1 + mov %r0, %l2 + mov %r0, %l3 + mov %r0, %l4 + mov %r0, %l5 + mov %r0, %l6 + mov %r0, %l7 + mov %r0, %o0 + mov %r0, %o1 + mov %r0, %o2 + mov %r0, %o3 + mov %r0, %o4 + mov %r0, %o5 + mov %r0, %o6 + mov %r0, %o7 +#endif + retry +.endm + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/regwin.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/regwin.h (revision 53ad43cce05b0004bca31a7c5d6822fc33686cf1) +++ kernel/arch/sparc64/include/arch/trap/regwin.h (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -79,127 +79,5 @@ #ifdef __ASSEMBLER__ - -/* - * Macro used by the nucleus and the primary context 0 during normal and other spills. - */ -.macro SPILL_NORMAL_HANDLER_KERNEL - stx %l0, [%sp + STACK_BIAS + L0_OFFSET] - stx %l1, [%sp + STACK_BIAS + L1_OFFSET] - stx %l2, [%sp + STACK_BIAS + L2_OFFSET] - stx %l3, [%sp + STACK_BIAS + L3_OFFSET] - stx %l4, [%sp + STACK_BIAS + L4_OFFSET] - stx %l5, [%sp + STACK_BIAS + L5_OFFSET] - stx %l6, [%sp + STACK_BIAS + L6_OFFSET] - stx %l7, [%sp + STACK_BIAS + L7_OFFSET] - stx %i0, [%sp + STACK_BIAS + I0_OFFSET] - stx %i1, [%sp + STACK_BIAS + I1_OFFSET] - stx %i2, [%sp + STACK_BIAS + I2_OFFSET] - stx %i3, [%sp + STACK_BIAS + I3_OFFSET] - stx %i4, [%sp + STACK_BIAS + I4_OFFSET] - stx %i5, [%sp + STACK_BIAS + I5_OFFSET] - stx %i6, [%sp + STACK_BIAS + I6_OFFSET] - stx %i7, [%sp + STACK_BIAS + I7_OFFSET] - saved - retry -.endm - -/* - * Macro used by the userspace during normal spills. - */ -.macro SPILL_NORMAL_HANDLER_USERSPACE - wr %g0, ASI_AIUP, %asi - stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi - stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi - stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi - stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi - stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi - stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi - stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi - stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi - stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi - stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi - stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi - stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi - stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi - stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi - stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi - stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi - saved - retry -.endm - -/* - * Macro used by the nucleus and the primary context 0 during normal fills. - */ -.macro FILL_NORMAL_HANDLER_KERNEL - ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 - ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 - ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 - ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 - ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 - ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 - ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 - ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 - ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 - ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 - ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 - ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 - ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 - ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 - ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 - ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 - restored - retry -.endm - -/* - * Macro used by the userspace during normal fills. - */ -.macro FILL_NORMAL_HANDLER_USERSPACE - wr %g0, ASI_AIUP, %asi - ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0 - ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1 - ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2 - ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3 - ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4 - ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5 - ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6 - ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7 - ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0 - ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1 - ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2 - ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3 - ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4 - ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5 - ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6 - ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7 - restored - retry -.endm - -.macro CLEAN_WINDOW_HANDLER - rdpr %cleanwin, %l0 - add %l0, 1, %l0 - wrpr %l0, 0, %cleanwin -#if defined(SUN4U) - mov %r0, %l0 - mov %r0, %l1 - mov %r0, %l2 - mov %r0, %l3 - mov %r0, %l4 - mov %r0, %l5 - mov %r0, %l6 - mov %r0, %l7 - mov %r0, %o0 - mov %r0, %o1 - mov %r0, %o2 - mov %r0, %o3 - mov %r0, %o4 - mov %r0, %o5 - mov %r0, %o6 - mov %r0, %o7 -#endif - retry -.endm +#include #endif /* __ASSEMBLER__ */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/mmu.S =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/mmu.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) +++ kernel/arch/sparc64/include/arch/trap/sun4u/mmu.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains fast MMU trap handlers. + */ + +.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER + /* + * First, try to refill TLB from TSB. + */ +#ifdef CONFIG_TSB + ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register + ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer + ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 + cmp %g1, %g4 ! is this the entry we are looking for? + bne,pn %xcc, 0f + nop + stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB + retry +#endif + +0: + wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2 + mov VA_IMMU_TAG_ACCESS, %g5 + ldxa [%g5] ASI_IMMU, %g5 ! read the faulting Context and VPN + PREEMPTIBLE_HANDLER exc_dispatch +.endm + +.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl + /* + * First, try to refill TLB from TSB. + */ + +#ifdef CONFIG_TSB + ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register + srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? + brz,pn %g2, 0f + ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer + ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 + cmp %g1, %g4 ! is this the entry we are looking for? + bne,pn %xcc, 0f + nop + stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB + retry +#endif + + /* + * Second, test if it is the portion of the kernel address space + * which is faulting. If that is the case, immediately create + * identity mapping for that page in DTLB. VPN 0 is excluded from + * this treatment. + * + * Note that branch-delay slots are used in order to save space. + */ +0: + sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 + wr %g0, ASI_DMMU, %asi + ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN + ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2 + andcc %g1, %g2, %g3 ! get Context + bnz %xcc, 0f ! Context is non-zero + andncc %g1, %g2, %g3 ! get page address into %g3 + bz %xcc, 0f ! page address is zero + ldx [%g7 + %lo(end_of_identity)], %g4 + cmp %g3, %g4 + bgeu %xcc, 0f + + ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 + add %g3, %g2, %g2 + stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page + retry + + /* + * Third, catch and handle special cases when the trap is caused by + * the userspace register window spill or fill handler. In case + * one of these two traps caused this trap, we just lower the trap + * level and service the DTLB miss. In the end, we restart + * the offending SAVE or RESTORE. + */ +0: +.if (\tl > 0) + wrpr %g0, 1, %tl +.endif + + /* + * Switch from the MM globals. + */ + wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + + mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2 + ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5 ! read the faulting Context and VPN + PREEMPTIBLE_HANDLER exc_dispatch +.endm + +.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl + /* + * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. + */ + +.if (\tl > 0) + wrpr %g0, 1, %tl +.endif + + /* + * Switch from the MM globals. + */ + wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + + mov TT_FAST_DATA_ACCESS_PROTECTION, %g2 + mov VA_DMMU_TAG_ACCESS, %g5 + ldxa [%g5] ASI_DMMU, %g5 ! read the faulting Context and VPN + PREEMPTIBLE_HANDLER exc_dispatch +.endm + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h (revision 53ad43cce05b0004bca31a7c5d6822fc33686cf1) +++ kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -56,114 +56,5 @@ #ifdef __ASSEMBLER__ - -.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER - /* - * First, try to refill TLB from TSB. - */ -#ifdef CONFIG_TSB - ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register - ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer - ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 - cmp %g1, %g4 ! is this the entry we are looking for? - bne,pn %xcc, 0f - nop - stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB - retry -#endif - -0: - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate - mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2 - mov VA_IMMU_TAG_ACCESS, %g5 - ldxa [%g5] ASI_IMMU, %g5 ! read the faulting Context and VPN - PREEMPTIBLE_HANDLER exc_dispatch -.endm - -.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl - /* - * First, try to refill TLB from TSB. - */ - -#ifdef CONFIG_TSB - ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register - srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? - brz,pn %g2, 0f - ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer - ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 - cmp %g1, %g4 ! is this the entry we are looking for? - bne,pn %xcc, 0f - nop - stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB - retry -#endif - - /* - * Second, test if it is the portion of the kernel address space - * which is faulting. If that is the case, immediately create - * identity mapping for that page in DTLB. VPN 0 is excluded from - * this treatment. - * - * Note that branch-delay slots are used in order to save space. - */ -0: - sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 - wr %g0, ASI_DMMU, %asi - ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN - ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2 - andcc %g1, %g2, %g3 ! get Context - bnz %xcc, 0f ! Context is non-zero - andncc %g1, %g2, %g3 ! get page address into %g3 - bz %xcc, 0f ! page address is zero - ldx [%g7 + %lo(end_of_identity)], %g4 - cmp %g3, %g4 - bgeu %xcc, 0f - - ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 - add %g3, %g2, %g2 - stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page - retry - - /* - * Third, catch and handle special cases when the trap is caused by - * the userspace register window spill or fill handler. In case - * one of these two traps caused this trap, we just lower the trap - * level and service the DTLB miss. In the end, we restart - * the offending SAVE or RESTORE. - */ -0: -.if (\tl > 0) - wrpr %g0, 1, %tl -.endif - - /* - * Switch from the MM globals. - */ - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate - - mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2 - ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5 ! read the faulting Context and VPN - PREEMPTIBLE_HANDLER exc_dispatch -.endm - -.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl - /* - * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. - */ - -.if (\tl > 0) - wrpr %g0, 1, %tl -.endif - - /* - * Switch from the MM globals. - */ - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate - - mov TT_FAST_DATA_ACCESS_PROTECTION, %g2 - mov VA_DMMU_TAG_ACCESS, %g5 - ldxa [%g5] ASI_DMMU, %g5 ! read the faulting Context and VPN - PREEMPTIBLE_HANDLER exc_dispatch -.endm - +#include #endif /* __ASSEMBLER__ */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/regwin.S =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/regwin.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) +++ kernel/arch/sparc64/include/arch/trap/sun4u/regwin.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ + +/* + * Macro used to spill userspace window to userspace window buffer. + * It can be either triggered from preemptible_handler doing SAVE + * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0 + * at (TL=0). + */ +.macro SPILL_TO_USPACE_WINDOW_BUFFER + stx %l0, [%g7 + L0_OFFSET] + stx %l1, [%g7 + L1_OFFSET] + stx %l2, [%g7 + L2_OFFSET] + stx %l3, [%g7 + L3_OFFSET] + stx %l4, [%g7 + L4_OFFSET] + stx %l5, [%g7 + L5_OFFSET] + stx %l6, [%g7 + L6_OFFSET] + stx %l7, [%g7 + L7_OFFSET] + stx %i0, [%g7 + I0_OFFSET] + stx %i1, [%g7 + I1_OFFSET] + stx %i2, [%g7 + I2_OFFSET] + stx %i3, [%g7 + I3_OFFSET] + stx %i4, [%g7 + I4_OFFSET] + stx %i5, [%g7 + I5_OFFSET] + stx %i6, [%g7 + I6_OFFSET] + stx %i7, [%g7 + I7_OFFSET] + add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7 + saved + retry +.endm + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h (revision 53ad43cce05b0004bca31a7c5d6822fc33686cf1) +++ kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -34,33 +34,5 @@ #ifdef __ASSEMBLER__ - -/* - * Macro used to spill userspace window to userspace window buffer. - * It can be either triggered from preemptible_handler doing SAVE - * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0 - * at (TL=0). - */ -.macro SPILL_TO_USPACE_WINDOW_BUFFER - stx %l0, [%g7 + L0_OFFSET] - stx %l1, [%g7 + L1_OFFSET] - stx %l2, [%g7 + L2_OFFSET] - stx %l3, [%g7 + L3_OFFSET] - stx %l4, [%g7 + L4_OFFSET] - stx %l5, [%g7 + L5_OFFSET] - stx %l6, [%g7 + L6_OFFSET] - stx %l7, [%g7 + L7_OFFSET] - stx %i0, [%g7 + I0_OFFSET] - stx %i1, [%g7 + I1_OFFSET] - stx %i2, [%g7 + I2_OFFSET] - stx %i3, [%g7 + I3_OFFSET] - stx %i4, [%g7 + I4_OFFSET] - stx %i5, [%g7 + I5_OFFSET] - stx %i6, [%g7 + I6_OFFSET] - stx %i7, [%g7 + I7_OFFSET] - add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7 - saved - retry -.endm - +#include #endif Index: kernel/arch/sparc64/include/arch/trap/sun4v/mmu.S =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/mmu.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) +++ kernel/arch/sparc64/include/arch/trap/sun4v/mmu.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains fast MMU trap handlers. + */ + +/* MMU fault status area data fault offset */ +#define FSA_DFA_OFFSET 0x48 + +/* MMU fault status area data context */ +#define FSA_DFC_OFFSET 0x50 + +/* offset of the target address within the TTE Data entry */ +#define TTE_DATA_TADDR_OFFSET 13 + +.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER + mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2 + clr %g5 ! XXX + PREEMPTIBLE_HANDLER exc_dispatch +.endm + +/* + * Handler of the Fast Data Access MMU Miss trap. If the trap occurred in the kernel + * (context 0), an identity mapping (with displacement) is installed. Otherwise + * a higher level service routine is called. + */ +.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl + mov SCRATCHPAD_MMU_FSA, %g1 + ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area + + /* read faulting context */ + add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context + ldxa [%g2] ASI_REAL, %g3 ! read the fault context + + /* read the faulting address */ + add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address + ldxa [%g2] ASI_REAL, %g1 ! read the fault address + srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary + sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 + + /* service by higher-level routine when context != 0 */ + brnz %g3, 0f + nop + /* exclude page number 0 from installing the identity mapping */ + brz %g1, 0f + nop + + /* exclude pages beyond the end of memory from the identity mapping */ + sethi %hi(end_of_identity), %g4 + ldx [%g4 + %lo(end_of_identity)], %g4 + cmp %g1, %g4 + bgeu %xcc, 0f + nop + + /* + * Installing the identity does not fit into 32 instructions, call + * a separate routine. The routine performs RETRY, hence the call never + * returns. + */ + ba,a %xcc, install_identity_mapping + +0: + + /* + * One of the scenarios in which this trap can occur is when the + * register window spill/fill handler accesses a memory which is not + * mapped. In such a case, this handler will be called from TL = 1. + * We handle the situation by pretending that the MMU miss occurred + * on TL = 0. Once the MMU miss trap is serviced, the instruction which + * caused the spill/fill trap is restarted, the spill/fill trap occurs, + * but this time its handler accesses memory which is mapped. + */ + .if (\tl > 0) + wrpr %g0, 1, %tl + .endif + + mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2 + + /* + * Save the faulting virtual page and faulting context to the %g5 + * register. The most significant 51 bits of the %g5 register will + * contain the virtual address which caused the fault truncated to the + * page boundary. The least significant 13 bits of the %g5 register + * will contain the number of the context in which the fault occurred. + * The value of the %g5 register will be stored in the istate structure + * for inspeciton by the higher level service routine. + */ + or %g1, %g3, %g5 + + PREEMPTIBLE_HANDLER exc_dispatch +.endm + +/* + * Handler of the Fast Data MMU Protection trap. Finds the trapping address + * and context and calls higher level service routine. + */ +.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl + /* + * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. + */ + .if (\tl > 0) + wrpr %g0, 1, %tl + .endif + + mov SCRATCHPAD_MMU_FSA, %g1 + ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area + + /* read faulting context */ + add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context + ldxa [%g2] ASI_REAL, %g3 ! read the fault context + + /* read the faulting address */ + add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address + ldxa [%g2] ASI_REAL, %g1 ! read the fault address + srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary + sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 + + mov TT_FAST_DATA_ACCESS_PROTECTION, %g2 + + /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */ + or %g1, %g3, %g5 + + PREEMPTIBLE_HANDLER exc_dispatch +.endm + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (revision 53ad43cce05b0004bca31a7c5d6822fc33686cf1) +++ kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -62,123 +62,5 @@ #ifdef __ASSEMBLER__ - -/* MMU fault status area data fault offset */ -#define FSA_DFA_OFFSET 0x48 - -/* MMU fault status area data context */ -#define FSA_DFC_OFFSET 0x50 - -/* offset of the target address within the TTE Data entry */ -#define TTE_DATA_TADDR_OFFSET 13 - -.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER - mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2 - clr %g5 ! XXX - PREEMPTIBLE_HANDLER exc_dispatch -.endm - -/* - * Handler of the Fast Data Access MMU Miss trap. If the trap occurred in the kernel - * (context 0), an identity mapping (with displacement) is installed. Otherwise - * a higher level service routine is called. - */ -.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl - mov SCRATCHPAD_MMU_FSA, %g1 - ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area - - /* read faulting context */ - add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context - ldxa [%g2] ASI_REAL, %g3 ! read the fault context - - /* read the faulting address */ - add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address - ldxa [%g2] ASI_REAL, %g1 ! read the fault address - srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary - sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 - - /* service by higher-level routine when context != 0 */ - brnz %g3, 0f - nop - /* exclude page number 0 from installing the identity mapping */ - brz %g1, 0f - nop - - /* exclude pages beyond the end of memory from the identity mapping */ - sethi %hi(end_of_identity), %g4 - ldx [%g4 + %lo(end_of_identity)], %g4 - cmp %g1, %g4 - bgeu %xcc, 0f - nop - - /* - * Installing the identity does not fit into 32 instructions, call - * a separate routine. The routine performs RETRY, hence the call never - * returns. - */ - ba,a %xcc, install_identity_mapping - -0: - - /* - * One of the scenarios in which this trap can occur is when the - * register window spill/fill handler accesses a memory which is not - * mapped. In such a case, this handler will be called from TL = 1. - * We handle the situation by pretending that the MMU miss occurred - * on TL = 0. Once the MMU miss trap is serviced, the instruction which - * caused the spill/fill trap is restarted, the spill/fill trap occurs, - * but this time its handler accesses memory which is mapped. - */ - .if (\tl > 0) - wrpr %g0, 1, %tl - .endif - - mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2 - - /* - * Save the faulting virtual page and faulting context to the %g5 - * register. The most significant 51 bits of the %g5 register will - * contain the virtual address which caused the fault truncated to the - * page boundary. The least significant 13 bits of the %g5 register - * will contain the number of the context in which the fault occurred. - * The value of the %g5 register will be stored in the istate structure - * for inspeciton by the higher level service routine. - */ - or %g1, %g3, %g5 - - PREEMPTIBLE_HANDLER exc_dispatch -.endm - -/* - * Handler of the Fast Data MMU Protection trap. Finds the trapping address - * and context and calls higher level service routine. - */ -.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl - /* - * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. - */ - .if (\tl > 0) - wrpr %g0, 1, %tl - .endif - - mov SCRATCHPAD_MMU_FSA, %g1 - ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area - - /* read faulting context */ - add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context - ldxa [%g2] ASI_REAL, %g3 ! read the fault context - - /* read the faulting address */ - add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address - ldxa [%g2] ASI_REAL, %g1 ! read the fault address - srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary - sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 - - mov TT_FAST_DATA_ACCESS_PROTECTION, %g2 - - /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */ - or %g1, %g3, %g5 - - PREEMPTIBLE_HANDLER exc_dispatch -.endm +#include #endif /* __ASSEMBLER__ */ Index: kernel/arch/sparc64/include/arch/trap/sun4v/regwin.S =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/regwin.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) +++ kernel/arch/sparc64/include/arch/trap/sun4v/regwin.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ + +/* + * Saves the contents of the current window to the userspace window buffer. + * Does not modify any register window registers, but updates pointer to the + * top of the userspace window buffer. + * + * Parameters: + * \tmpreg1 global register to be used for scratching purposes + * \tmpreg2 global register to be used for scratching purposes + */ +.macro SAVE_TO_USPACE_WBUF tmpreg1, tmpreg2 + set SCRATCHPAD_WBUF, \tmpreg2 + ldxa [\tmpreg2] ASI_SCRATCHPAD, \tmpreg1 + stx %l0, [\tmpreg1 + L0_OFFSET] + stx %l1, [\tmpreg1 + L1_OFFSET] + stx %l2, [\tmpreg1 + L2_OFFSET] + stx %l3, [\tmpreg1 + L3_OFFSET] + stx %l4, [\tmpreg1 + L4_OFFSET] + stx %l5, [\tmpreg1 + L5_OFFSET] + stx %l6, [\tmpreg1 + L6_OFFSET] + stx %l7, [\tmpreg1 + L7_OFFSET] + stx %i0, [\tmpreg1 + I0_OFFSET] + stx %i1, [\tmpreg1 + I1_OFFSET] + stx %i2, [\tmpreg1 + I2_OFFSET] + stx %i3, [\tmpreg1 + I3_OFFSET] + stx %i4, [\tmpreg1 + I4_OFFSET] + stx %i5, [\tmpreg1 + I5_OFFSET] + stx %i6, [\tmpreg1 + I6_OFFSET] + stx %i7, [\tmpreg1 + I7_OFFSET] + add \tmpreg1, STACK_WINDOW_SAVE_AREA_SIZE, \tmpreg1 + stxa \tmpreg1, [\tmpreg2] ASI_SCRATCHPAD +.endm + +/* + * Macro used to spill userspace window to userspace window buffer. + * It is triggered from normal kernel code doing SAVE when + * OTHERWIN>0 at (TL=0). + */ +.macro SPILL_TO_USPACE_WINDOW_BUFFER + SAVE_TO_USPACE_WBUF %g7, %g4 + saved + retry +.endm + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h (revision 53ad43cce05b0004bca31a7c5d6822fc33686cf1) +++ kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -35,48 +35,5 @@ #ifdef __ASSEMBLER__ - -/* - * Saves the contents of the current window to the userspace window buffer. - * Does not modify any register window registers, but updates pointer to the - * top of the userspace window buffer. - * - * Parameters: - * \tmpreg1 global register to be used for scratching purposes - * \tmpreg2 global register to be used for scratching purposes - */ -.macro SAVE_TO_USPACE_WBUF tmpreg1, tmpreg2 - set SCRATCHPAD_WBUF, \tmpreg2 - ldxa [\tmpreg2] ASI_SCRATCHPAD, \tmpreg1 - stx %l0, [\tmpreg1 + L0_OFFSET] - stx %l1, [\tmpreg1 + L1_OFFSET] - stx %l2, [\tmpreg1 + L2_OFFSET] - stx %l3, [\tmpreg1 + L3_OFFSET] - stx %l4, [\tmpreg1 + L4_OFFSET] - stx %l5, [\tmpreg1 + L5_OFFSET] - stx %l6, [\tmpreg1 + L6_OFFSET] - stx %l7, [\tmpreg1 + L7_OFFSET] - stx %i0, [\tmpreg1 + I0_OFFSET] - stx %i1, [\tmpreg1 + I1_OFFSET] - stx %i2, [\tmpreg1 + I2_OFFSET] - stx %i3, [\tmpreg1 + I3_OFFSET] - stx %i4, [\tmpreg1 + I4_OFFSET] - stx %i5, [\tmpreg1 + I5_OFFSET] - stx %i6, [\tmpreg1 + I6_OFFSET] - stx %i7, [\tmpreg1 + I7_OFFSET] - add \tmpreg1, STACK_WINDOW_SAVE_AREA_SIZE, \tmpreg1 - stxa \tmpreg1, [\tmpreg2] ASI_SCRATCHPAD -.endm - -/* - * Macro used to spill userspace window to userspace window buffer. - * It is triggered from normal kernel code doing SAVE when - * OTHERWIN>0 at (TL=0). - */ -.macro SPILL_TO_USPACE_WINDOW_BUFFER - SAVE_TO_USPACE_WBUF %g7, %g4 - saved - retry -.endm - +#include #endif Index: kernel/arch/sparc64/include/arch/trap/trap_table.S =================================================================== --- kernel/arch/sparc64/include/arch/trap/trap_table.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) +++ kernel/arch/sparc64/include/arch/trap/trap_table.S (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** @file + */ + +.macro SAVE_GLOBALS + mov %g1, %l1 + mov %g2, %l2 + mov %g3, %l3 + mov %g4, %l4 + mov %g5, %l5 + mov %g6, %l6 + mov %g7, %l7 +.endm + +.macro RESTORE_GLOBALS + mov %l1, %g1 + mov %l2, %g2 + mov %l3, %g3 + mov %l4, %g4 + mov %l5, %g5 + mov %l6, %g6 + mov %l7, %g7 +.endm + +.macro PREEMPTIBLE_HANDLER f + sethi %hi(\f), %g1 + ba %xcc, preemptible_handler + or %g1, %lo(\f), %g1 +.endm + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/trap_table.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/trap_table.h (revision 53ad43cce05b0004bca31a7c5d6822fc33686cf1) +++ kernel/arch/sparc64/include/arch/trap/trap_table.h (revision 8f3230ec92ab67da1d0e4a321fb627cdd307b255) @@ -43,46 +43,6 @@ #define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE) -#ifndef __ASSEMBLER__ - -#include - -struct trap_table_entry { - uint8_t octets[TRAP_TABLE_ENTRY_SIZE]; -} __attribute__ ((packed)); - -typedef struct trap_table_entry trap_table_entry_t; - -extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT]; -extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT]; - -#endif /* !__ASSEMBLER__ */ - #ifdef __ASSEMBLER__ -.macro SAVE_GLOBALS - mov %g1, %l1 - mov %g2, %l2 - mov %g3, %l3 - mov %g4, %l4 - mov %g5, %l5 - mov %g6, %l6 - mov %g7, %l7 -.endm - -.macro RESTORE_GLOBALS - mov %l1, %g1 - mov %l2, %g2 - mov %l3, %g3 - mov %l4, %g4 - mov %l5, %g5 - mov %l6, %g6 - mov %l7, %g7 -.endm - -.macro PREEMPTIBLE_HANDLER f - sethi %hi(\f), %g1 - ba %xcc, preemptible_handler - or %g1, %lo(\f), %g1 -.endm - +#include #endif /* __ASSEMBLER__ */