Changeset 8ec4144 in mainline
- Timestamp:
- 2012-09-02T19:50:46Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 2673b3b, 5321e48, ac31040
- Parents:
- f5299fa
- Files:
-
- 2 added
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
HelenOS.config
rf5299fa r8ec4144 457 457 ! [(CONFIG_HID_IN=generic|CONFIG_HID_IN=serial)&PLATFORM=ia64&MACHINE=i460GX] CONFIG_NS16550 (y/n) 458 458 459 % Support for ARM926 on-chip UART 460 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=integratorcp] CONFIG_ARM926_UART (y/n) 461 459 462 % Support for Samsung S3C24XX on-chip UART 460 463 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_UART (y/n) … … 482 485 483 486 % Serial line input module 484 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM= ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)487 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y) 485 488 486 489 % EGA support -
kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
rf5299fa r8ec4144 38 38 #include <console/chardev.h> 39 39 #include <genarch/drivers/pl050/pl050.h> 40 #include <genarch/drivers/arm926_uart/arm926_uart.h> 40 41 #include <genarch/kbrd/kbrd.h> 42 #include <genarch/srln/srln.h> 41 43 #include <console/console.h> 42 44 #include <sysinfo/sysinfo.h> … … 53 55 #include <print.h> 54 56 57 55 58 #define SDRAM_SIZE (sdram[((*(uint32_t *)(ICP_CMCR+ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2)]) 56 static icp_hw_map_t icp_hw_map; 57 static irq_t icp_timer_irq; 59 60 static struct { 61 icp_hw_map_t hw_map; 62 irq_t timer_irq; 63 arm926_uart_t uart; 64 } icp; 65 66 67 58 68 struct arm_machine_ops icp_machine_ops = { 59 69 icp_init, … … 88 98 void icp_vga_init(void) 89 99 { 90 *(uint32_t*)((char *)(icp _hw_map.cmcr)+0x14) = 0xA05F0000;91 *(uint32_t*)((char *)(icp _hw_map.cmcr)+0x1C) = 0x12C11000;92 *(uint32_t*)icp _hw_map.vga = 0x3F1F3F9C;93 *(uint32_t*)((char *)(icp _hw_map.vga) + 0x4) = 0x080B61DF;94 *(uint32_t*)((char *)(icp _hw_map.vga) + 0x8) = 0x067F3800;95 *(uint32_t*)((char *)(icp _hw_map.vga) + 0x10) = ICP_FB;96 *(uint32_t *)((char *)(icp _hw_map.vga) + 0x1C) = 0x182B;97 *(uint32_t*)((char *)(icp _hw_map.cmcr)+0xC) = 0x33805000;100 *(uint32_t*)((char *)(icp.hw_map.cmcr)+0x14) = 0xA05F0000; 101 *(uint32_t*)((char *)(icp.hw_map.cmcr)+0x1C) = 0x12C11000; 102 *(uint32_t*)icp.hw_map.vga = 0x3F1F3F9C; 103 *(uint32_t*)((char *)(icp.hw_map.vga) + 0x4) = 0x080B61DF; 104 *(uint32_t*)((char *)(icp.hw_map.vga) + 0x8) = 0x067F3800; 105 *(uint32_t*)((char *)(icp.hw_map.vga) + 0x10) = ICP_FB; 106 *(uint32_t *)((char *)(icp.hw_map.vga) + 0x1C) = 0x182B; 107 *(uint32_t*)((char *)(icp.hw_map.cmcr)+0xC) = 0x33805000; 98 108 99 109 } … … 102 112 static inline uint32_t icp_irqc_get_sources(void) 103 113 { 104 return *((uint32_t *) icp _hw_map.irqc);114 return *((uint32_t *) icp.hw_map.irqc); 105 115 } 106 116 … … 112 122 static inline void icp_irqc_mask(uint32_t irq) 113 123 { 114 *((uint32_t *) icp _hw_map.irqc_mask) = (1 << irq);124 *((uint32_t *) icp.hw_map.irqc_mask) = (1 << irq); 115 125 } 116 126 … … 122 132 static inline void icp_irqc_unmask(uint32_t irq) 123 133 { 124 *((uint32_t *) icp _hw_map.irqc_unmask) |= (1 << irq);125 } 126 127 /** Initializes icp _hw_map. */134 *((uint32_t *) icp.hw_map.irqc_unmask) |= (1 << irq); 135 } 136 137 /** Initializes icp.hw_map. */ 128 138 void icp_init(void) 129 139 { 130 icp _hw_map.uart = km_map(ICP_UART, PAGE_SIZE,131 PAGE_WRITE | PAGE_NOT_CACHEABLE); 132 icp _hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_NOT_CACHEABLE);133 icp _hw_map.kbd_stat = icp_hw_map.kbd_ctrl + ICP_KBD_STAT;134 icp _hw_map.kbd_data = icp_hw_map.kbd_ctrl + ICP_KBD_DATA;135 icp _hw_map.kbd_intstat = icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;136 icp _hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE,137 PAGE_WRITE | PAGE_NOT_CACHEABLE); 138 icp _hw_map.rtc1_load = icp_hw_map.rtc + ICP_RTC1_LOAD_OFFSET;139 icp _hw_map.rtc1_read = icp_hw_map.rtc + ICP_RTC1_READ_OFFSET;140 icp _hw_map.rtc1_ctl = icp_hw_map.rtc + ICP_RTC1_CTL_OFFSET;141 icp _hw_map.rtc1_intrclr = icp_hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET;142 icp _hw_map.rtc1_bgload = icp_hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET;143 icp _hw_map.rtc1_intrstat = icp_hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;144 145 icp _hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE,146 PAGE_WRITE | PAGE_NOT_CACHEABLE); 147 icp _hw_map.irqc_mask = icp_hw_map.irqc + ICP_IRQC_MASK_OFFSET;148 icp _hw_map.irqc_unmask = icp_hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;149 icp _hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE,150 PAGE_WRITE | PAGE_NOT_CACHEABLE); 151 icp _hw_map.sdramcr = icp_hw_map.cmcr + ICP_SDRAMCR_OFFSET;152 icp _hw_map.vga = km_map(ICP_VGA, PAGE_SIZE,140 icp.hw_map.uart = km_map(ICP_UART, PAGE_SIZE, 141 PAGE_WRITE | PAGE_NOT_CACHEABLE); 142 icp.hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_NOT_CACHEABLE); 143 icp.hw_map.kbd_stat = icp.hw_map.kbd_ctrl + ICP_KBD_STAT; 144 icp.hw_map.kbd_data = icp.hw_map.kbd_ctrl + ICP_KBD_DATA; 145 icp.hw_map.kbd_intstat = icp.hw_map.kbd_ctrl + ICP_KBD_INTR_STAT; 146 icp.hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE, 147 PAGE_WRITE | PAGE_NOT_CACHEABLE); 148 icp.hw_map.rtc1_load = icp.hw_map.rtc + ICP_RTC1_LOAD_OFFSET; 149 icp.hw_map.rtc1_read = icp.hw_map.rtc + ICP_RTC1_READ_OFFSET; 150 icp.hw_map.rtc1_ctl = icp.hw_map.rtc + ICP_RTC1_CTL_OFFSET; 151 icp.hw_map.rtc1_intrclr = icp.hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET; 152 icp.hw_map.rtc1_bgload = icp.hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET; 153 icp.hw_map.rtc1_intrstat = icp.hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET; 154 155 icp.hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE, 156 PAGE_WRITE | PAGE_NOT_CACHEABLE); 157 icp.hw_map.irqc_mask = icp.hw_map.irqc + ICP_IRQC_MASK_OFFSET; 158 icp.hw_map.irqc_unmask = icp.hw_map.irqc + ICP_IRQC_UNMASK_OFFSET; 159 icp.hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE, 160 PAGE_WRITE | PAGE_NOT_CACHEABLE); 161 icp.hw_map.sdramcr = icp.hw_map.cmcr + ICP_SDRAMCR_OFFSET; 162 icp.hw_map.vga = km_map(ICP_VGA, PAGE_SIZE, 153 163 PAGE_WRITE | PAGE_NOT_CACHEABLE); 154 164 … … 163 173 { 164 174 icp_irqc_mask(ICP_TIMER_IRQ); 165 *((uint32_t*) icp _hw_map.rtc1_load) = frequency;166 *((uint32_t*) icp _hw_map.rtc1_bgload) = frequency;167 *((uint32_t*) icp _hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;175 *((uint32_t*) icp.hw_map.rtc1_load) = frequency; 176 *((uint32_t*) icp.hw_map.rtc1_bgload) = frequency; 177 *((uint32_t*) icp.hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE; 168 178 icp_irqc_unmask(ICP_TIMER_IRQ); 169 179 } … … 171 181 static irq_ownership_t icp_timer_claim(irq_t *irq) 172 182 { 173 if (icp _hw_map.rtc1_intrstat) {174 *((uint32_t*) icp _hw_map.rtc1_intrclr) = 1;183 if (icp.hw_map.rtc1_intrstat) { 184 *((uint32_t*) icp.hw_map.rtc1_intrclr) = 1; 175 185 return IRQ_ACCEPT; 176 186 } else … … 199 209 static void icp_timer_irq_init(void) 200 210 { 201 irq_initialize(&icp _timer_irq);202 icp _timer_irq.devno = device_assign_devno();203 icp _timer_irq.inr = ICP_TIMER_IRQ;204 icp _timer_irq.claim = icp_timer_claim;205 icp _timer_irq.handler = icp_timer_irq_handler;206 207 irq_register(&icp _timer_irq);211 irq_initialize(&icp.timer_irq); 212 icp.timer_irq.devno = device_assign_devno(); 213 icp.timer_irq.inr = ICP_TIMER_IRQ; 214 icp.timer_irq.claim = icp_timer_claim; 215 icp.timer_irq.handler = icp_timer_irq_handler; 216 217 irq_register(&icp.timer_irq); 208 218 } 209 219 … … 230 240 231 241 if (hw_map_init_called) { 232 *size = (sdram[((*(uint32_t *)icp _hw_map.sdramcr &242 *size = (sdram[((*(uint32_t *)icp.hw_map.sdramcr & 233 243 ICP_SDRAM_MASK) >> 2)]); 234 244 } else { … … 304 314 stdout_wire(fbdev); 305 315 #endif 316 #ifdef CONFIG_ARM926_UART 317 if (arm926_uart_init(&icp.uart, ARM926_UART0_IRQ, 318 ARM926_UART0_BASE_ADDRESS, sizeof(arm926_uart_regs_t))) 319 stdout_wire(&icp.uart.outdev); 320 #endif 306 321 } 307 322 … … 310 325 311 326 pl050_t *pl050 = malloc(sizeof(pl050_t), FRAME_ATOMIC); 312 pl050->status = (ioport8_t *)icp _hw_map.kbd_stat;313 pl050->data = (ioport8_t *)icp _hw_map.kbd_data;314 pl050->ctrl = (ioport8_t *)icp _hw_map.kbd_ctrl;327 pl050->status = (ioport8_t *)icp.hw_map.kbd_stat; 328 pl050->data = (ioport8_t *)icp.hw_map.kbd_data; 329 pl050->ctrl = (ioport8_t *)icp.hw_map.kbd_ctrl; 315 330 316 331 pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ); … … 335 350 ICP_KBD); 336 351 352 #ifdef CONFIG_ARM926_UART 353 srln_instance_t *srln_instance = srln_init(); 354 if (srln_instance) { 355 indev_t *sink = stdin_wire(); 356 indev_t *srln = srln_wire(srln_instance, sink); 357 arm926_uart_input_wire(&icp.uart, srln); 358 icp_irqc_unmask(ARM926_UART0_IRQ); 359 } 360 #endif 337 361 } 338 362 -
kernel/genarch/Makefile.inc
rf5299fa r8ec4144 91 91 endif 92 92 93 ifeq ($(CONFIG_ARM926_UART),y) 94 GENARCH_SOURCES += \ 95 genarch/src/drivers/arm926_uart/arm926_uart.c 96 endif 97 93 98 ifeq ($(CONFIG_S3C24XX_IRQC),y) 94 99 GENARCH_SOURCES += \
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