Index: kernel/arch/ia64/include/asm.h
===================================================================
--- kernel/arch/ia64/include/asm.h	(revision 71eef11b8afe2eec0d0ac48ea6fce51144cb5b0c)
+++ kernel/arch/ia64/include/asm.h	(revision 8ccd2ea277c15d5df7f5e27ff901bafaa18515df)
@@ -41,9 +41,10 @@
 
 
-#define IA64_IOSPACE_ADDRESS 0xE0000FFFFC000000ULL
+#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
 static inline void  outb(uint64_t port,uint8_t v)
 {
 	*((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
+
 	asm volatile ("mf\n" ::: "memory");
 }
@@ -53,4 +54,5 @@
 {
 	asm volatile ("mf\n" ::: "memory");
+
 	return *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
 }
Index: kernel/arch/ia64/include/drivers/ega.h
===================================================================
--- kernel/arch/ia64/include/drivers/ega.h	(revision 71eef11b8afe2eec0d0ac48ea6fce51144cb5b0c)
+++ kernel/arch/ia64/include/drivers/ega.h	(revision 8ccd2ea277c15d5df7f5e27ff901bafaa18515df)
@@ -37,5 +37,5 @@
 #define KERN_ia64_EGA_H
 
-#define VIDEORAM (0xE0000000000B8000LL)
+#define VIDEORAM (0xe0020000000B8000LL)
 
 #define ROW		80
Index: kernel/arch/ia64/include/mm/page.h
===================================================================
--- kernel/arch/ia64/include/mm/page.h	(revision 71eef11b8afe2eec0d0ac48ea6fce51144cb5b0c)
+++ kernel/arch/ia64/include/mm/page.h	(revision 8ccd2ea277c15d5df7f5e27ff901bafaa18515df)
@@ -48,4 +48,6 @@
 /** Bit width of the TLB-locked portion of kernel address space. */
 #define KERNEL_PAGE_WIDTH		28	/* 256M */
+#define IO_PAGE_WIDTH			26	/* 64M */
+
 
 #define PPN_SHIFT			12
Index: kernel/arch/ia64/src/mm/frame.c
===================================================================
--- kernel/arch/ia64/src/mm/frame.c	(revision 71eef11b8afe2eec0d0ac48ea6fce51144cb5b0c)
+++ kernel/arch/ia64/src/mm/frame.c	(revision 8ccd2ea277c15d5df7f5e27ff901bafaa18515df)
@@ -42,11 +42,13 @@
  * for real ia64 systems that provide memory map.
  */
-#define MEMORY_SIZE	(512 * 1024 * 1024)
-#define ROM_BASE	0xa0000
-#define ROM_SIZE	(384 * 1024)
+#define MEMORY_SIZE	(64 * 1024 * 1024)
+#define MEMORY_BASE	(64 * 1024 * 1024)
 
+#define ROM_BASE	0xa0000               //For ski
+#define ROM_SIZE	(384 * 1024)          //For ski
+void poke_char(int x,int y,char ch, char c);
 void frame_arch_init(void)
 {
-	zone_create(0, SIZE2FRAMES(MEMORY_SIZE), 1, 0);
+	zone_create(MEMORY_BASE >> FRAME_WIDTH, SIZE2FRAMES(MEMORY_SIZE), (MEMORY_SIZE) >> FRAME_WIDTH, 0);
 	
 	/*
@@ -54,4 +56,5 @@
 	 */
 	frame_mark_unavailable(ADDR2PFN(ROM_BASE), SIZE2FRAMES(ROM_SIZE));
+	
 }
 
Index: kernel/arch/ia64/src/start.S
===================================================================
--- kernel/arch/ia64/src/start.S	(revision 71eef11b8afe2eec0d0ac48ea6fce51144cb5b0c)
+++ kernel/arch/ia64/src/start.S	(revision 8ccd2ea277c15d5df7f5e27ff901bafaa18515df)
@@ -36,6 +36,13 @@
 #define PS_SHIFT 2
 
-#define KERNEL_TRANSLATION_I 0x0010000000000661
-#define KERNEL_TRANSLATION_D 0x0010000000000661
+#define KERNEL_TRANSLATION_I  0x0010000000000661
+#define KERNEL_TRANSLATION_D  0x0010000000000661
+#define KERNEL_TRANSLATION_VIO 0x0010000000000671
+#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 
+#define VIO_OFFSET            0x0002000000000000
+
+#define IO_OFFSET             0x0001000000000000
+
+
 
 .section K_TEXT_START, "ax"
@@ -47,27 +54,68 @@
 	.auto
 
+	mov psr.l = r0
+	srlz.i
+	srlz.d
+
 	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
+
 
 	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 	mov r9 = rr[r8]
+
+
 	movl r10 = (RR_MASK)
 	and r9 = r10, r9
 	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
 	or  r9 = r10, r9
+
+
 	mov rr[r8] = r9
+
+
 
 	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 	mov cr.ifa = r8
-	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
-	mov cr.itir = r10
+
+	
+	mov r11 = cr.itir ;;
+	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
+	or r10 =r10 , r11  ;;
+	mov cr.itir = r10;;
+
+	
 	movl r10 = (KERNEL_TRANSLATION_I)
 	itr.i itr[r0] = r10
+
+	
 	movl r10 = (KERNEL_TRANSLATION_D)
 	itr.d dtr[r0] = r10
 
+
+	movl r7 = 1
+	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
+	mov cr.ifa = r8
+	movl r10 = (KERNEL_TRANSLATION_VIO)
+	itr.d dtr[r7] = r10
+
+
+	mov r11 = cr.itir ;;
+	movl r10 = ~0xfc;;
+	and r10 =r10 , r11  ;;
+	movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
+	or r10 =r10 , r11  ;;
+	mov cr.itir = r10;;
+
+
+	movl r7 = 2
+	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
+	mov cr.ifa = r8
+	movl r10 = (KERNEL_TRANSLATION_IO)
+	itr.d dtr[r7] = r10
+
+
+
+
 	# initialize PSR
-	mov psr.l = r0
-	srlz.i
-	srlz.d
 	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
 	mov r9 = psr