Index: kernel/arch/ia32/Makefile.inc
===================================================================
--- kernel/arch/ia32/Makefile.inc	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/Makefile.inc	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -64,4 +64,8 @@
 endif
 
+ifeq ($(PROCESSOR),i486)
+	CMN2 = -march=i486
+endif
+
 ifeq ($(PROCESSOR),core)
 	CMN2 = -march=prescott
Index: kernel/arch/ia32/include/asm.h
===================================================================
--- kernel/arch/ia32/include/asm.h	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/include/asm.h	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -311,4 +311,5 @@
 }
 
+#ifndef PROCESSOR_i486
 /** Write to MSR */
 NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
@@ -321,4 +322,5 @@
 	);
 }
+#endif
 
 NO_TRACE static inline uint64_t read_msr(uint32_t msr)
Index: kernel/arch/ia32/include/atomic.h
===================================================================
--- kernel/arch/ia32/include/atomic.h	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/include/atomic.h	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -121,5 +121,7 @@
 	asm volatile (
 		"0:\n"
+#ifndef PROCESSOR_i486
 		"pause\n"        /* Pentium 4's HT love this instruction */
+#endif
 		"mov %[count], %[tmp]\n"
 		"testl %[tmp], %[tmp]\n"
Index: kernel/arch/ia32/include/cycle.h
===================================================================
--- kernel/arch/ia32/include/cycle.h	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/include/cycle.h	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -40,4 +40,7 @@
 NO_TRACE static inline uint64_t get_cycle(void)
 {
+#ifdef PROCESSOR_i486
+	return 0;
+#else
 	uint64_t v;
 	
@@ -48,4 +51,5 @@
 	
 	return v;
+#endif
 }
 
Index: kernel/arch/ia32/src/asm.S
===================================================================
--- kernel/arch/ia32/src/asm.S	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/src/asm.S	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -405,5 +405,11 @@
 	xorl %eax, %eax
 	cmpl $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%esp)
+#ifdef PROCESSOR_i486
+	jz 0f
+	movl %eax, %ebp
+0:
+#else
 	cmovnzl %eax, %ebp
+#endif
 
 	movl %ebp, ISTATE_OFFSET_EBP_FRAME(%esp)
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -118,9 +118,11 @@
 		);
 	}
-	
+
+#ifndef PROCESSOR_i486
 	if (CPU->arch.fi.bits.sep) {
 		/* Setup fast SYSENTER/SYSEXIT syscalls */
 		syscall_setup_cpu();
 	}
+#endif
 }
 
Index: kernel/arch/ia32/src/proc/scheduler.c
===================================================================
--- kernel/arch/ia32/src/proc/scheduler.c	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/src/proc/scheduler.c	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -60,8 +60,10 @@
 	uintptr_t kstk = (uintptr_t) &THREAD->kstack[STACK_SIZE];
 	
+#ifndef PROCESSOR_i486
 	if (CPU->arch.fi.bits.sep) {
 		/* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
 		write_msr(IA32_MSR_SYSENTER_ESP, kstk - sizeof(istate_t));
 	}
+#endif
 	
 	/* Set kernel stack for CPL3 -> CPL0 switch via interrupt */
Index: kernel/arch/ia32/src/syscall.c
===================================================================
--- kernel/arch/ia32/src/syscall.c	(revision f4fa6d97622246b092c84b7d84bfeffa10cbe6a4)
+++ kernel/arch/ia32/src/syscall.c	(revision 8c15255808b8cb7f5be4dc66647bfc281a76c041)
@@ -39,4 +39,5 @@
 #include <arch/pm.h>
 
+#ifndef PROCESSOR_i486
 /** Enable & setup support for SYSENTER/SYSEXIT */
 void syscall_setup_cpu(void)
@@ -49,4 +50,5 @@
 	write_msr(IA32_MSR_SYSENTER_EIP, (uint32_t) sysenter_handler);
 }
+#endif
 
 /** @}