Changeset 8b863a62 in mainline for boot/arch


Ignore:
Timestamp:
2014-04-16T17:14:06Z (12 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f857e8b
Parents:
dba3e2c (diff), 70b570c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes

Location:
boot/arch
Files:
14 added
13 edited

Legend:

Unmodified
Added
Removed

  • boot/arch/amd64/Makefile.inc

    rdba3e2c r8b863a62  
    2828
    2929RD_SRVS_ESSENTIAL += \
     30        $(USPACE_PATH)/srv/audio/hound/hound \
     31        $(USPACE_PATH)/srv/devman/devman \
    3032        $(USPACE_PATH)/srv/hw/irc/apic/apic \
    3133        $(USPACE_PATH)/srv/hw/irc/i8259/i8259
    3234
    33 RD_SRVS_NON_ESSENTIAL += \
    34         $(USPACE_PATH)/srv/bd/ata_bd/ata_bd
    3535
    36 RD_DRVS += \
     36RD_DRVS_ESSENTIAL += \
    3737        infrastructure/rootpc \
     38        block/ata_bd \
    3839        bus/pci/pciintel \
    3940        bus/isa \
     41        audio/sb16 \
    4042        char/i8042 \
     43        char/ps2mouse \
     44        char/xtkbd
     45
     46RD_DRVS_NON_ESSENTIAL += \
    4147        char/ns8250 \
    42         char/ps2mouse \
    43         char/xtkbd \
    4448        time/cmos-rtc \
    4549        bus/usb/ehci\
    … …  
    5761        bus/isa
    5862
     63RD_APPS_ESSENTIAL += \
     64        $(USPACE_PATH)/app/edit/edit \
     65        $(USPACE_PATH)/app/mixerctl/mixerctl \
     66        $(USPACE_PATH)/app/wavplay/wavplay \
     67       
    5968BOOT_OUTPUT = $(ROOT_PATH)/image.iso
    6069PREBUILD = $(INITRD).img

  • boot/arch/arm32/Makefile.inc

    rdba3e2c r8b863a62  
    4343endif
    4444
     45ifeq ($(MACHINE), raspberrypi)
     46        BOOT_OUTPUT = image.boot
     47        POST_OUTPUT = $(ROOT_PATH)/uImage.bin   
     48        LADDR = 0x00008000
     49        SADDR = 0x00008000
     50        POSTBUILD = Makefile.uboot           
     51endif
     52
    4553BFD_NAME = elf32-littlearm
    4654BFD_OUTPUT = $(BFD_NAME)
    … …  
    5765endif
    5866
    59 RD_DRVS += \
     67RD_DRVS_ESSENTIAL += \
    6068        infrastructure/rootamdm37x \
    6169        fb/amdm37x_dispc \

  • boot/arch/arm32/include/arch.h

    rdba3e2c r8b863a62  
    4646#elif defined MACHINE_beaglebone
    4747#define BOOT_BASE       0x80000000
     48#elif defined MACHINE_raspberrypi
     49#define BOOT_BASE       0x00008000
    4850#else
    4951#define BOOT_BASE       0x00000000

  • boot/arch/arm32/include/main.h

    rdba3e2c r8b863a62  
    7575#define ICP_SCONS_ADDR          0x16000000
    7676
     77/** Raspberry PI serial console registers */
     78#define BCM2835_UART0_BASE      0x20201000
     79#define BCM2835_UART0_DR        (BCM2835_UART0_BASE + 0x00)
     80#define BCM2835_UART0_FR        (BCM2835_UART0_BASE + 0x18)
     81#define BCM2835_UART0_ILPR      (BCM2835_UART0_BASE + 0x20)
     82#define BCM2835_UART0_IBRD      (BCM2835_UART0_BASE + 0x24)
     83#define BCM2835_UART0_FBRD      (BCM2835_UART0_BASE + 0x28)
     84#define BCM2835_UART0_LCRH      (BCM2835_UART0_BASE + 0x2C)
     85#define BCM2835_UART0_CR        (BCM2835_UART0_BASE + 0x30)
     86#define BCM2835_UART0_ICR       (BCM2835_UART0_BASE + 0x44)
     87
     88#define BCM2835_UART0_FR_TXFF   (1 << 5)
     89#define BCM2835_UART0_LCRH_FEN  (1 << 4)
     90#define BCM2835_UART0_LCRH_WL8  ((1 << 5) | (1 << 6))
     91#define BCM2835_UART0_CR_UARTEN (1 << 0)
     92#define BCM2835_UART0_CR_TXE    (1 << 8)
     93#define BCM2835_UART0_CR_RXE    (1 << 9)
     94
     95
     96
    7797extern void bootstrap(void);
    7898

  • boot/arch/arm32/include/mm.h

    rdba3e2c r8b863a62  
    6868#define AM335x_RAM_END     0xC0000000
    6969
     70/** Start of ram memory on BCM2835 */
     71#define BCM2835_RAM_START   0
     72/** End of ram memory on BCM2835 */
     73#define BCM2835_RAM_END     0x20000000
    7074
    7175/* Page table level 0 entry - "section" format is used

  • boot/arch/arm32/src/asm.S

    rdba3e2c r8b863a62  
    5656jump_to_kernel:
    5757        #
    58         # TODO
    5958        # Make sure that the I-cache, D-cache and memory are mutually coherent
    6059        # before passing control to the copied code.
    … …  
    6867#define CP15_C1_BP              11
    6968#define CP15_C1_DC              2
    70         # Disable I-cache and D-cache before the kernel is started.
     69
     70
     71#ifndef PROCESSOR_ARCH_armv7_a
    7172        mrc     p15, 0, r4, c1, c0, 0
     73       
     74        # D-cache before the kernel is started.
    7275        bic     r4, r4, #(1 << CP15_C1_DC)
     76
     77        # Disable I-cache and Branche predictors.
    7378        bic     r4, r4, #(1 << CP15_C1_IC)
    7479        bic     r4, r4, #(1 << CP15_C1_BP)
     80       
    7581        mcr     p15, 0, r4, c1, c0, 0
     82#endif
     83
    7684
    7785       
    … …  
    8189#else
    8290        #cp15 dsb, r4 is ignored (should be zero)
     91        mov r4, #0
    8392        mcr p15, 0, r4, c7, c10, 4
    8493#endif
    8594       
    8695        # Clean ICache and BPredictors, r4 ignored (SBZ)
     96        mov r4, #0
    8797        mcr p15, 0, r4, c7, c5, 0
    8898        nop

  • boot/arch/arm32/src/main.c

    rdba3e2c r8b863a62  
    5353extern void *bdata_end;
    5454
    55 
    56 static inline void invalidate_icache(void)
    57 {
    58         /* ICIALLU Invalidate entire ICache */
    59         asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
    60 }
    61 
    62 static inline void invalidate_dcache(void *address, size_t size)
    63 {
    64         const uintptr_t addr = (uintptr_t)address;
    65         /* DCIMVAC - invalidate by address to the point of coherence */
    66         for (uintptr_t a = addr; a < addr + size; a += 4) {
    67                 asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
    68         }
    69 }
    70 
    7155static inline void clean_dcache_poc(void *address, size_t size)
    7256{
    7357        const uintptr_t addr = (uintptr_t)address;
    74         /* DCCMVAC - clean by address to the point of coherence */
    7558        for (uintptr_t a = addr; a < addr + size; a += 4) {
     59                /* DCCMVAC - clean by address to the point of coherence */
    7660                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
    7761        }
    … …  
    8266void bootstrap(void)
    8367{
    84         /* Make sure  we run in memory code when caches are enabled,
    85          * make sure we read memory data too. This part is ARMv7 specific as
    86          * ARMv7 no longer invalidates caches on restart.
    87          * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
    88         invalidate_icache();
    89         invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
    90 
    9168        /* Enable MMU and caches */
    9269        mmu_start();
    … …  
    10582                    components[i].start, components[i].name, components[i].inflated,
    10683                    components[i].size);
    107                 invalidate_dcache(components[i].start, components[i].size);
    10884        }
    10985       
    … …  
    148124                        halt();
    149125                }
     126                /* Make sure data are in the memory, ICache will need them */
    150127                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    151128        }

  • boot/arch/arm32/src/mm.c

    rdba3e2c r8b863a62  
    3737#include <arch/asm.h>
    3838#include <arch/mm.h>
     39#include <arch/cp15.h>
     40
     41#ifdef PROCESSOR_ARCH_armv7_a
     42static unsigned log2(unsigned val)
     43{
     44        unsigned log = 0;
     45        while (val >> log++);
     46        return log - 2;
     47}
     48
     49static void dcache_invalidate_level(unsigned level)
     50{
     51        CSSELR_write(level << 1);
     52        const uint32_t ccsidr = CCSIDR_read();
     53        const unsigned sets = CCSIDR_SETS(ccsidr);
     54        const unsigned ways = CCSIDR_WAYS(ccsidr);
     55        const unsigned line_log = CCSIDR_LINESIZE_LOG(ccsidr);
     56        const unsigned set_shift = line_log;
     57        const unsigned way_shift = 32 - log2(ways);
     58
     59        for (unsigned k = 0; k < ways; ++k)
     60                for (unsigned j = 0; j < sets; ++j) {
     61                        const uint32_t val = (level << 1) |
     62                            (j << set_shift) | (k << way_shift);
     63                        DCISW_write(val);
     64                }
     65}
     66
     67/** invalidate all dcaches -- armv7 */
     68static void cache_invalidate(void)
     69{
     70        const uint32_t cinfo = CLIDR_read();
     71        for (unsigned i = 0; i < 7; ++i) {
     72                switch (CLIDR_CACHE(i, cinfo))
     73                {
     74                case CLIDR_DCACHE_ONLY:
     75                case CLIDR_SEP_CACHE:
     76                case CLIDR_UNI_CACHE:
     77                        dcache_invalidate_level(i);
     78                }
     79        }
     80        asm volatile ( "dsb\n" );
     81        ICIALLU_write(0);
     82        asm volatile ( "isb\n" );
     83}
     84#endif
    3985
    4086/** Disable the MMU */
    … …  
    60106static inline int section_cacheable(pfn_t section)
    61107{
     108        const unsigned long address = section << PTE_SECTION_SHIFT;
    62109#ifdef MACHINE_gta02
    63         unsigned long address = section << PTE_SECTION_SHIFT;
    64 
    65         if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
    66                 return 0;
    67         else
     110        if (address < GTA02_IOMEM_START || address >= GTA02_IOMEM_END)
    68111                return 1;
    69112#elif defined MACHINE_beagleboardxm
    70         const unsigned long address = section << PTE_SECTION_SHIFT;
    71113        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
    72114                return 1;
    73115#elif defined MACHINE_beaglebone
    74         const unsigned long address = section << PTE_SECTION_SHIFT;
    75116        if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
    76117                return 1;
    77 #endif
    78         return 0;
     118#elif defined MACHINE_raspberrypi
     119        if (address < BCM2835_RAM_END)
     120                return 1;
     121#endif
     122        return address * 0;
    79123}
    80124
    … …  
    95139{
    96140        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    97         pte->bufferable = 1;
    98         pte->cacheable = section_cacheable(frame);
    99141        pte->xn = 0;
    100142        pte->domain = 0;
    101143        pte->should_be_zero_1 = 0;
    102144        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
     145#ifdef PROCESSOR_ARCH_armv7_a
     146        /*
     147         * Keeps this setting in sync with memory type attributes in:
     148         * init_boot_pt (boot/arch/arm32/src/mm.c)
     149         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
     150         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
     151         */
     152        pte->tex = section_cacheable(frame) ? 5 : 0;
     153        pte->cacheable = section_cacheable(frame) ? 0 : 0;
     154        pte->bufferable = section_cacheable(frame) ? 1 : 0;
     155#else
     156        pte->bufferable = 1;
     157        pte->cacheable = section_cacheable(frame);
    103158        pte->tex = 0;
     159#endif
    104160        pte->access_permission_1 = 0;
    105161        pte->shareable = 0;
    … …  
    113169static void init_boot_pt(void)
    114170{
    115         const pfn_t split_page = PTL0_ENTRIES;
    116         /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    117         pfn_t page;
    118         for (page = 0; page < split_page; page++)
     171        /*
     172         * Create 1:1 virtual-physical mapping.
     173         * Physical memory on BBxM a BBone starts at 2GB
     174         * boundary, icp has a memory mirror at 2GB.
     175         * (ARM Integrator Core Module User guide ch. 6.3,  p. 6-7)
     176         * gta02 somehow works (probably due to limited address size),
     177         * s3c2442b manual ch. 5, p.5-1:
     178         * "Address space: 128Mbytes per bank (total 1GB/8 banks)"
     179         */
     180        for (pfn_t page = 0; page < PTL0_ENTRIES; ++page)
    119181                init_ptl0_section(&boot_pt[page], page);
    120        
    121         asm volatile (
    122                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    123                 :: [pt] "r" (boot_pt)
    124         );
     182
     183        /*
     184         * Tell MMU page might be cached. Keeps this setting in sync
     185         * with memory type attributes in:
     186         * init_ptl0_section (boot/arch/arm32/src/mm.c)
     187         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
     188         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
     189         */
     190        uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
     191        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
     192        TTBR0_write(val);
    125193}
    126194
    … …  
    141209                 * we disable caches before jumping to kernel
    142210                 * so this is safe for all archs.
     211                 * Enable VMSAv6 the bit (23) is only writable on ARMv6.
     212                 * (and QEMU)
    143213                 */
     214#ifdef PROCESSOR_ARCH_armv6
     215                "ldr r1, =0x00801805\n"
     216#else
    144217                "ldr r1, =0x00001805\n"
     218#endif
    145219               
    146220                "orr r0, r0, r1\n"
    … …  
    160234void mmu_start() {
    161235        disable_paging();
     236#ifdef PROCESSOR_ARCH_armv7_a
     237        /* Make sure we run in memory code when caches are enabled,
     238         * make sure we read memory data too. This part is ARMv7 specific as
     239         * ARMv7 no longer invalidates caches on restart.
     240         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
     241        cache_invalidate();
     242#endif
    162243        init_boot_pt();
    163244        enable_paging();

  • boot/arch/arm32/src/putchar.c

    rdba3e2c r8b863a62  
    122122#endif
    123123
     124#ifdef MACHINE_raspberrypi
     125
     126static int raspi_init;
     127
     128static inline void write32(uint32_t addr, uint32_t data)
     129{
     130        *(volatile uint32_t *)(addr) = data;
     131}
     132
     133static inline uint32_t read32(uint32_t addr)
     134{
     135        return *(volatile uint32_t *)(addr);
     136}
     137
     138static void scons_init_raspi(void)
     139{
     140        write32(BCM2835_UART0_CR, 0x0);         /* Disable UART */
     141        write32(BCM2835_UART0_ICR, 0x7f);       /* Clear interrupts */
     142        write32(BCM2835_UART0_IBRD, 1);         /* Set integer baud rate */
     143        write32(BCM2835_UART0_FBRD, 40);        /* Set fractional baud rate */
     144        write32(BCM2835_UART0_LCRH,
     145                BCM2835_UART0_LCRH_FEN |        /* Enable FIFOs */
     146                BCM2835_UART0_LCRH_WL8);        /* Word length: 8 */
     147        write32(BCM2835_UART0_CR,
     148                BCM2835_UART0_CR_UARTEN |       /* Enable UART */
     149                BCM2835_UART0_CR_TXE |          /* Enable TX */
     150                BCM2835_UART0_CR_RXE);          /* Enable RX */
     151}
     152
     153static void scons_sendb_raspi(uint8_t byte)
     154{
     155        if (!raspi_init) {
     156                scons_init_raspi();
     157                raspi_init = 1;
     158        }
     159
     160        while (read32(BCM2835_UART0_FR) & BCM2835_UART0_FR_TXFF);
     161
     162        write32(BCM2835_UART0_DR, byte);
     163}
     164#endif
     165
    124166/** Send a byte to the serial console.
    125167 *
    … …  
    139181#ifdef MACHINE_integratorcp
    140182        scons_sendb_icp(byte);
     183#endif
     184#ifdef MACHINE_raspberrypi
     185        scons_sendb_raspi(byte);
    141186#endif
    142187}

  • boot/arch/ia64/Makefile.inc

    rdba3e2c r8b863a62  
    7474        arch/$(BARCH)/src/ski.c
    7575endif
     76
     77RD_DRVS_ESSENTIAL += \
     78        infrastructure/rootpc \
     79        bus/pci/pciintel \
     80        bus/isa \
     81        char/i8042 \
     82        char/xtkbd
     83
     84RD_DRVS_NON_ESSENTIAL += \
     85        char/ns8250 \
     86        time/cmos-rtc \
     87        bus/usb/ehci\
     88        bus/usb/ohci \
     89        bus/usb/uhci \
     90        bus/usb/uhcirh \
     91        bus/usb/usbflbk \
     92        bus/usb/usbhub \
     93        bus/usb/usbhid \
     94        bus/usb/usbmast \
     95        bus/usb/usbmid \
     96        bus/usb/vhc
     97
     98RD_DRV_CFG += \
     99        bus/isa
     100

  • boot/arch/mips32/Makefile.inc

    rdba3e2c r8b863a62  
    5050endif
    5151
     52ifeq ($(MACHINE), $(filter $(MACHINE),bmalta lmalta))
     53        RD_DRVS_ESSENTIAL += \
     54                infrastructure/rootmalta \
     55                block/ata_bd \
     56                bus/pci/pciintel \
     57                bus/isa \
     58                char/i8042 \
     59                char/ps2mouse \
     60                char/xtkbd
     61
     62        RD_DRV_CFG += \
     63                bus/isa
     64endif
    5265
    5366SOURCES = \

  • boot/arch/ppc32/Makefile.inc

    rdba3e2c r8b863a62  
    4242        $(USPACE_PATH)/srv/hw/bus/cuda_adb/cuda_adb
    4343
    44 RD_DRVS += \
     44RD_DRVS_ESSENTIAL += \
    4545        infrastructure/rootmac \
    4646        bus/pci/pciintel \

  • boot/arch/sparc64/src/asm.S

    rdba3e2c r8b863a62  
    3030#include <arch/arch.h>
    3131
     32#if defined(PROCESSOR_us) || defined(PROCESSOR_us3)
    3233#define ICACHE_SIZE       8192
    3334#define ICACHE_LINE_SIZE  32
    3435#define ICACHE_SET_BIT    (1 << 13)
    3536#define ASI_ICACHE_TAG    0x67
     37#endif  /* PROCESSOR_us || PROCESSOR_us3 */
    3638
    3739.register %g2, #scratch
    … …  
    134136# Flush I-cache
    135137icache_flush:
     138#if defined(PROCESSOR_us) || defined(PROCESSOR_us3)
    136139        set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
    137140        stxa %g0, [%g1] ASI_ICACHE_TAG
    … …  
    149152       
    150153        nop
     154#else
     155        // TODO: sun4v
     156        retl
     157        nop
     158#endif  /* PROCESSOR_us || PROCESSOR_us3 */
    151159
    152160.global ofw
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