Index: kernel/arch/ia64/include/asm.h =================================================================== --- kernel/arch/ia64/include/asm.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/asm.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -44,26 +44,27 @@ #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL -static inline void outb(ioport_t port,uint8_t v) -{ - *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; - - asm volatile ("mf\n" ::: "memory"); -} - -static inline void outw(ioport_t port,uint16_t v) -{ - *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; - - asm volatile ("mf\n" ::: "memory"); -} - -static inline void outl(ioport_t port,uint32_t v) -{ - *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; - - asm volatile ("mf\n" ::: "memory"); -} - - +static inline void outb(ioport_t port, uint8_t v) +{ + *((uint8_t *)(IA64_IOSPACE_ADDRESS + + ((port & 0xfff) | ((port >> 2) << 12)))) = v; + + asm volatile ("mf\n" ::: "memory"); +} + +static inline void outw(ioport_t port, uint16_t v) +{ + *((uint16_t *)(IA64_IOSPACE_ADDRESS + + ((port & 0xfff) | ((port >> 2) << 12)))) = v; + + asm volatile ("mf\n" ::: "memory"); +} + +static inline void outl(ioport_t port, uint32_t v) +{ + *((uint32_t *)(IA64_IOSPACE_ADDRESS + + ((port & 0xfff) | ((port >> 2) << 12)))) = v; + + asm volatile ("mf\n" ::: "memory"); +} static inline uint8_t inb(ioport_t port) @@ -71,5 +72,6 @@ asm volatile ("mf\n" ::: "memory"); - return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); + return *((uint8_t *)(IA64_IOSPACE_ADDRESS + + ((port & 0xfff) | ((port >> 2) << 12)))); } @@ -78,5 +80,6 @@ asm volatile ("mf\n" ::: "memory"); - return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 )))); + return *((uint16_t *)(IA64_IOSPACE_ADDRESS + + ((port & 0xffE) | ((port >> 2) << 12)))); } @@ -85,8 +88,7 @@ asm volatile ("mf\n" ::: "memory"); - return *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); -} - - + return *((uint32_t *)(IA64_IOSPACE_ADDRESS + + ((port & 0xfff) | ((port >> 2) << 12)))); +} /** Return base address of current stack @@ -343,5 +345,6 @@ extern void asm_delay_loop(uint32_t t); -extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc); +extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t, + uint64_t, uint64_t); #endif Index: kernel/arch/ia64/include/atomic.h =================================================================== --- kernel/arch/ia64/include/atomic.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/atomic.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -38,8 +38,8 @@ /** Atomic addition. * - * @param val Atomic value. - * @param imm Value to add. + * @param val Atomic value. + * @param imm Value to add. * - * @return Value before addition. + * @return Value before addition. */ static inline long atomic_add(atomic_t *val, int imm) @@ -47,5 +47,6 @@ long v; - asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm)); + asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), + "+m" (val->count) : "i" (imm)); return v; @@ -57,7 +58,7 @@ asm volatile ( - "movl %0=0x01;;\n" - "xchg8 %0=%1,%0;;\n" - : "=r" (v),"+m" (val->count) + "movl %0 = 0x01;;\n" + "xchg8 %0 = %1, %0;;\n" + : "=r" (v), "+m" (val->count) ); @@ -66,12 +67,33 @@ -static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } -static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } +static inline void atomic_inc(atomic_t *val) +{ + atomic_add(val, 1); +} -static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1) + 1; } -static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1) - 1; } +static inline void atomic_dec(atomic_t *val) +{ + atomic_add(val, -1); +} -static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1); } -static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1); } +static inline long atomic_preinc(atomic_t *val) +{ + return atomic_add(val, 1) + 1; +} + +static inline long atomic_predec(atomic_t *val) +{ + return atomic_add(val, -1) - 1; +} + +static inline long atomic_postinc(atomic_t *val) +{ + return atomic_add(val, 1); +} + +static inline long atomic_postdec(atomic_t *val) +{ + return atomic_add(val, -1); +} #endif Index: kernel/arch/ia64/include/bootinfo.h =================================================================== --- kernel/arch/ia64/include/bootinfo.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/bootinfo.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -69,5 +69,4 @@ unsigned int wakeup_intno; int hello_configured; - } bootinfo_t; Index: kernel/arch/ia64/include/cpu.h =================================================================== --- kernel/arch/ia64/include/cpu.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/cpu.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -84,13 +84,10 @@ - -static inline void ipi_send_ipi(int id,int eid,int intno) +static inline void ipi_send_ipi(int id, int eid, int intno) { - (bootinfo->sapic)[2*(id*256+eid)]=intno; + (bootinfo->sapic)[2 * (id * 256 + eid)] = intno; srlz_d(); } - - #endif Index: kernel/arch/ia64/include/debug.h =================================================================== --- kernel/arch/ia64/include/debug.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/debug.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -1,4 +1,4 @@ /* - * Copyright (c) 2005 + * Copyright (c) 2005 Ondrej Palkovsky * All rights reserved. * Index: kernel/arch/ia64/include/interrupt.h =================================================================== --- kernel/arch/ia64/include/interrupt.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/interrupt.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -54,6 +54,6 @@ #define VECTOR_TLB_SHOOTDOWN_IPI 0xf0 #define INTERRUPT_TIMER 255 -#define IRQ_KBD (0x01+LEGACY_INTERRUPT_BASE) -#define IRQ_MOUSE (0x0c+LEGACY_INTERRUPT_BASE) +#define IRQ_KBD (0x01 + LEGACY_INTERRUPT_BASE) +#define IRQ_MOUSE (0x0c + LEGACY_INTERRUPT_BASE) #define INTERRUPT_SPURIOUS 15 #define LEGACY_INTERRUPT_BASE 0x20 @@ -118,5 +118,5 @@ /* * The following variables are defined only for break_instruction - * handler. + * handler. */ uint64_t in0; @@ -154,5 +154,4 @@ extern void disabled_fp_register(uint64_t vector, istate_t *istate); - #endif Index: kernel/arch/ia64/include/mm/page.h =================================================================== --- kernel/arch/ia64/include/mm/page.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/mm/page.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -52,9 +52,9 @@ - -/** Staticly mapped IO spaces - offsets to 0xe...00 of virtual adresses -becauce of "minimal virtual bits implemented is 51" -it is possible to have here values up to 0x0007000000000000 -*/ +/* + * Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses + * because of "minimal virtual bits implemented is 51" it is possible to + * have values up to 0x0007000000000000 + */ /* Firmware area (bellow 4GB in phys mem) */ @@ -62,8 +62,6 @@ /* Legacy IO space */ #define IO_OFFSET 0x0001000000000000 -/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/ +/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */ #define VIO_OFFSET 0x0002000000000000 - - @@ -82,6 +80,6 @@ #define REGION_REGISTERS 8 -#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<arch.iomap=NULL;} +#define task_create_arch(t) { (t)->arch.iomap = NULL; } #define task_destroy_arch(t) Index: kernel/arch/ia64/include/register.h =================================================================== --- kernel/arch/ia64/include/register.h (revision fb69f39c1c7a3f85d8a9f3789fe0ddf2fa266ec4) +++ kernel/arch/ia64/include/register.h (revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9) @@ -41,9 +41,9 @@ #define PSR_PK_MASK 0x8000 -#define PSR_DT_MASK (1<<17) -#define PSR_RT_MASK (1<<27) - -#define PSR_DFL_MASK (1<<18) -#define PSR_DFH_MASK (1<<19) +#define PSR_DT_MASK (1 << 17) +#define PSR_RT_MASK (1 << 27) + +#define PSR_DFL_MASK (1 << 18) +#define PSR_DFH_MASK (1 << 19) #define PSR_IT_MASK 0x0000001000000000