Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision ef5de6de5ee6aded0e5af29f536b20fd00228502)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision 8b4d6cbc48b833752f89ebc4578be4f2b25bc3b9)
@@ -93,5 +93,5 @@
 /** Invalidate entries belonging to an address space.
  *
- * @param asid Address space identifier.
+ * @param asid		Address space identifier.
  */
 void tlb_invalidate_asid(asid_t asid)
@@ -132,48 +132,43 @@
 	
 	switch (b) {
-	case 0: /*cnt 1-3*/
+	case 0: /* cnt 1 - 3 */
 		ps = PAGE_WIDTH;
 		break;
-	case 1: /*cnt 4-15*/
-		ps = PAGE_WIDTH+2;
-		va &= ~((1<<ps)-1);
-		break;
-	case 2: /*cnt 16-63*/
-		ps = PAGE_WIDTH+4;
-		va &= ~((1<<ps)-1);
-		break;
-	case 3: /*cnt 64-255*/
-		ps = PAGE_WIDTH+6;
-		va &= ~((1<<ps)-1);
-		break;
-	case 4: /*cnt 256-1023*/
-		ps = PAGE_WIDTH+8;
-		va &= ~((1<<ps)-1);
-		break;
-	case 5: /*cnt 1024-4095*/
-		ps = PAGE_WIDTH+10;
-		va &= ~((1<<ps)-1);
-		break;
-	case 6: /*cnt 4096-16383*/
-		ps = PAGE_WIDTH+12;
-		va &= ~((1<<ps)-1);
-		break;
-	case 7: /*cnt 16384-65535*/
-	case 8: /*cnt 65536-(256K-1)*/
-		ps = PAGE_WIDTH+14;
-		va &= ~((1<<ps)-1);
+	case 1: /* cnt 4 - 15 */
+		ps = PAGE_WIDTH + 2;
+		va &= ~((1 << ps) - 1);
+		break;
+	case 2: /* cnt 16 - 63 */
+		ps = PAGE_WIDTH + 4;
+		va &= ~((1 << ps) - 1);
+		break;
+	case 3: /* cnt 64 - 255 */
+		ps = PAGE_WIDTH + 6;
+		va &= ~((1 << ps) - 1);
+		break;
+	case 4: /* cnt 256 - 1023 */
+		ps = PAGE_WIDTH + 8;
+		va &= ~((1 << ps) - 1);
+		break;
+	case 5: /* cnt 1024 - 4095 */
+		ps = PAGE_WIDTH + 10;
+		va &= ~((1 << ps) - 1);
+		break;
+	case 6: /* cnt 4096 - 16383 */
+		ps = PAGE_WIDTH + 12;
+		va &= ~((1 << ps) - 1);
+		break;
+	case 7: /* cnt 16384 - 65535 */
+	case 8: /* cnt 65536 - (256K - 1) */
+		ps = PAGE_WIDTH + 14;
+		va &= ~((1 << ps) - 1);
 		break;
 	default:
-		ps=PAGE_WIDTH+18;
-		va&=~((1<<ps)-1);
-		break;
-	}
-	for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps))	{
-		asm volatile (
-			"ptc.l %0,%1;;"
-			:
-			: "r" (va), "r" (ps<<2)
-		);
-	}
+		ps = PAGE_WIDTH + 18;
+		va &= ~((1 << ps) - 1);
+		break;
+	}
+	for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
+		asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2));
 	srlz_d();
 	srlz_i();
@@ -188,7 +183,8 @@
 /** Insert data into data translation cache.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param va		Virtual page address.
+ * @param asid		Address space identifier.
+ * @param entry		The rest of TLB entry as required by TLB insertion
+ * 			format.
  */
 void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
@@ -199,7 +195,8 @@
 /** Insert data into instruction translation cache.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param va		Virtual page address.
+ * @param asid		Address space identifier.
+ * @param entry		The rest of TLB entry as required by TLB insertion
+ * 			format.
  */
 void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
@@ -210,8 +207,10 @@
 /** Insert data into instruction or data translation cache.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
+ * @param va		Virtual page address.
+ * @param asid		Address space identifier.
+ * @param entry		The rest of TLB entry as required by TLB insertion
+ * 			format.
+ * @param dtc		If true, insert into data translation cache, use
+ * 			instruction translation cache otherwise.
  */
 void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
@@ -236,17 +235,18 @@
 	
 	asm volatile (
-		"mov r8=psr;;\n"
+		"mov r8 = psr;;\n"
 		"rsm %0;;\n"   			/* PSR_IC_MASK */
 		"srlz.d;;\n"
 		"srlz.i;;\n"
-		"mov cr.ifa=%1\n"		/* va */
-		"mov cr.itir=%2;;\n"		/* entry.word[1] */
-		"cmp.eq p6,p7 = %4,r0;;\n"	/* decide between itc and dtc */ 
+		"mov cr.ifa = %1\n"		/* va */
+		"mov cr.itir = %2;;\n"		/* entry.word[1] */
+		"cmp.eq p6,p7 = %4,r0;;\n"	/* decide between itc and dtc */
 		"(p6) itc.i %3;;\n"
 		"(p7) itc.d %3;;\n"
-		"mov psr.l=r8;;\n"
+		"mov psr.l = r8;;\n"
 		"srlz.d;;\n"
 		:
-		: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
+		: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
+		    "r" (entry.word[0]), "r" (dtc)
 		: "p6", "p7", "r8"
 	);
@@ -261,10 +261,12 @@
 /** Insert data into instruction translation register.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param tr Translation register.
- */
-void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+ * @param va		Virtual page address.
+ * @param asid		Address space identifier.
+ * @param entry		The rest of TLB entry as required by TLB insertion
+ * 			format.
+ * @param tr		Translation register.
+ */
+void
+itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
 {
 	tr_mapping_insert(va, asid, entry, false, tr);
@@ -273,10 +275,12 @@
 /** Insert data into data translation register.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param tr Translation register.
- */
-void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+ * @param va		Virtual page address.
+ * @param asid		Address space identifier.
+ * @param entry		The rest of TLB entry as required by TLB insertion
+ * 			format.
+ * @param tr		Translation register.
+ */
+void
+dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
 {
 	tr_mapping_insert(va, asid, entry, true, tr);
@@ -285,11 +289,15 @@
 /** Insert data into instruction or data translation register.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param dtr If true, insert into data translation register, use instruction translation register otherwise.
- * @param tr Translation register.
- */
-void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
+ * @param va		Virtual page address.
+ * @param asid		Address space identifier.
+ * @param entry		The rest of TLB entry as required by TLB insertion
+ * 			format.
+ * @param dtr		If true, insert into data translation register, use
+ * 			instruction translation register otherwise.
+ * @param tr		Translation register.
+ */
+void
+tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
+    index_t tr)
 {
 	region_register rr;
@@ -312,17 +320,18 @@
 
 	asm volatile (
-		"mov r8=psr;;\n"
+		"mov r8 = psr;;\n"
 		"rsm %0;;\n"			/* PSR_IC_MASK */
 		"srlz.d;;\n"
 		"srlz.i;;\n"
-		"mov cr.ifa=%1\n"        	/* va */		 
-		"mov cr.itir=%2;;\n"		/* entry.word[1] */ 
-		"cmp.eq p6,p7=%5,r0;;\n"	/* decide between itr and dtr */
-		"(p6) itr.i itr[%4]=%3;;\n"
-		"(p7) itr.d dtr[%4]=%3;;\n"
-		"mov psr.l=r8;;\n"
+		"mov cr.ifa = %1\n"        	/* va */		 
+		"mov cr.itir = %2;;\n"		/* entry.word[1] */ 
+		"cmp.eq p6,p7 = %5,r0;;\n"	/* decide between itr and dtr */
+		"(p6) itr.i itr[%4] = %3;;\n"
+		"(p7) itr.d dtr[%4] = %3;;\n"
+		"mov psr.l = r8;;\n"
 		"srlz.d;;\n"
 		:
-		: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
+		: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
+		    "r" (entry.word[0]), "r" (tr), "r" (dtr)
 		: "p6", "p7", "r8"
 	);
@@ -337,10 +346,13 @@
 /** Insert data into DTLB.
  *
- * @param page Virtual page address including VRN bits.
- * @param frame Physical frame address.
- * @param dtr If true, insert into data translation register, use data translation cache otherwise.
- * @param tr Translation register if dtr is true, ignored otherwise.
- */
-void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr)
+ * @param page		Virtual page address including VRN bits.
+ * @param frame		Physical frame address.
+ * @param dtr		If true, insert into data translation register, use data
+ * 			translation cache otherwise.
+ * @param tr		Translation register if dtr is true, ignored otherwise.
+ */
+void
+dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
+    index_t tr)
 {
 	tlb_entry_t entry;
@@ -368,10 +380,10 @@
  * Purge DTR entries used by the kernel.
  *
- * @param page Virtual page address including VRN bits.
- * @param width Width of the purge in bits.
+ * @param page		Virtual page address including VRN bits.
+ * @param width		Width of the purge in bits.
  */
 void dtr_purge(uintptr_t page, count_t width)
 {
-	asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
+	asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
 }
 
@@ -379,5 +391,5 @@
 /** Copy content of PTE into data translation cache.
  *
- * @param t PTE.
+ * @param t		PTE.
  */
 void dtc_pte_copy(pte_t *t)
@@ -405,5 +417,5 @@
 /** Copy content of PTE into instruction translation cache.
  *
- * @param t PTE.
+ * @param t		PTE.
  */
 void itc_pte_copy(pte_t *t)
@@ -432,6 +444,6 @@
 /** Instruction TLB fault handler for faults with VHPT turned off.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector		Interruption vector.
+ * @param istate		Structure with saved interruption state.
  */
 void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
@@ -462,41 +474,43 @@
 		if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
 			fault_if_from_uspace(istate,"Page fault at %p",va);
-			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-		}
-	}
-}
-
-
+			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+			    istate->cr_iip);
+		}
+	}
+}
 
 static int is_io_page_accessible(int page)
 {
-	if(TASK->arch.iomap) return bitmap_get(TASK->arch.iomap,page);
-	else return 0;
+	if (TASK->arch.iomap)
+		return bitmap_get(TASK->arch.iomap,page);
+	else
+		return 0;
 }
 
 #define IO_FRAME_BASE 0xFFFFC000000
 
-/** There is special handling of memmaped lagacy io, because
- * of 4KB sized access
- * only for userspace
- *
- * @param va virtual address of page fault
- * @param istate Structure with saved interruption state.
- *
- *
- * @return 1 on success, 0 on fail
+/**
+ * There is special handling of memory mapped legacy io, because of 4KB sized
+ * access for userspace.
+ *
+ * @param va		Virtual address of page fault.
+ * @param istate	Structure with saved interruption state.
+ *
+ * @return		One on success, zero on failure.
  */
 static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
 {
-	if((va >= IO_OFFSET ) && (va < IO_OFFSET + (1<<IO_PAGE_WIDTH)))
-		if(TASK){
-			
-			uint64_t io_page=(va &  ((1<<IO_PAGE_WIDTH)-1)) >> (USPACE_IO_PAGE_WIDTH);
-			if(is_io_page_accessible(io_page)){
-				uint64_t page,frame;
-
-				page = IO_OFFSET + (1 << USPACE_IO_PAGE_WIDTH) * io_page;
-				frame = IO_FRAME_BASE + (1 << USPACE_IO_PAGE_WIDTH) * io_page;
-
+	if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) {
+		if (TASK) {
+			uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>
+			    USPACE_IO_PAGE_WIDTH;
+
+			if (is_io_page_accessible(io_page)) {
+				uint64_t page, frame;
+
+				page = IO_OFFSET +
+				    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
+				frame = IO_FRAME_BASE +
+				    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
 
 				tlb_entry_t entry;
@@ -505,8 +519,8 @@
 				entry.word[1] = 0;
 	
-				entry.p = true;			/* present */
+				entry.p = true;		/* present */
 				entry.ma = MA_UNCACHEABLE;		
-				entry.a = true;			/* already accessed */
-				entry.d = true;			/* already dirty */
+				entry.a = true;		/* already accessed */
+				entry.d = true;		/* already dirty */
 				entry.pl = PL_USER;
 				entry.ar = AR_READ | AR_WRITE;
@@ -516,24 +530,18 @@
 				dtc_mapping_insert(page, TASK->as->asid, entry);
 				return 1;
-			}else {
-				fault_if_from_uspace(istate,"IO access fault at %p",va);
-				return 0;
-			}		
-		} else 
-			return 0;
-	else 
-		return 0;
+			} else {
+				fault_if_from_uspace(istate,
+				    "IO access fault at %p", va);
+			}
+		}
+	}
 		
 	return 0;
-
-}
-
-
-
+}
 
 /** Data TLB fault handler for faults with VHPT turned off.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector	Interruption vector.
+ * @param istate	Structure with saved interruption state.
  */
 void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
@@ -569,11 +577,14 @@
 	} else {
 		page_table_unlock(AS, true);
-		if (try_memmap_io_insertion(va,istate)) return;
-		/*
-		 * Forward the page fault to the address space page fault handler.
+		if (try_memmap_io_insertion(va, istate))
+			return;
+		/*
+		 * Forward the page fault to the address space page fault 
+		 * handler.
 		 */
 		if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
 			fault_if_from_uspace(istate,"Page fault at %p",va);
-			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+			    istate->cr_iip);
 		}
 	}
@@ -584,6 +595,6 @@
  * This fault should not occur.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector	Interruption vector.
+ * @param istate	Structure with saved interruption state.
  */
 void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
@@ -594,6 +605,6 @@
 /** Data Dirty bit fault handler.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector	Interruption vector.
+ * @param istate	Structure with saved interruption state.
  */
 void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
@@ -621,7 +632,6 @@
 		if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
 			fault_if_from_uspace(istate,"Page fault at %p",va);
-			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-			t->d = true;
-			dtc_pte_copy(t);
+			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+			    istate->cr_iip);
 		}
 	}
@@ -631,6 +641,6 @@
 /** Instruction access bit fault handler.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector	Interruption vector.
+ * @param istate	Structure with saved interruption state.
  */
 void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
@@ -657,8 +667,7 @@
 	} else {
 		if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
-			fault_if_from_uspace(istate,"Page fault at %p",va);
-			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-			t->a = true;
-			itc_pte_copy(t);
+			fault_if_from_uspace(istate, "Page fault at %p", va);
+			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+			    istate->cr_iip);
 		}
 	}
@@ -694,8 +703,7 @@
 	} else {
 		if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-			fault_if_from_uspace(istate,"Page fault at %p",va);
-			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-			t->a = true;
-			itc_pte_copy(t);
+			fault_if_from_uspace(istate, "Page fault at %p", va);
+			panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+			    istate->cr_iip);
 		}
 	}
@@ -736,5 +744,5 @@
 		page_table_unlock(AS, true);
 		if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-			fault_if_from_uspace(istate,"Page fault at %p",va);
+			fault_if_from_uspace(istate, "Page fault at %p", va);
 			panic("%s: va=%p, rid=%d\n", __func__, va, rid);
 		}
