Index: kernel/arch/arm32/include/mm/page.h
===================================================================
--- kernel/arch/arm32/include/mm/page.h	(revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe)
+++ kernel/arch/arm32/include/mm/page.h	(revision 8b243f295e54de841c17a2606bdc9a2fe484dbbb)
@@ -56,11 +56,12 @@
 #ifdef KERNEL
 
+/* Number of entries in each level. */
 #define PTL0_ENTRIES_ARCH 	(2 << 12)	/* 4096 */
 #define PTL1_ENTRIES_ARCH 	0
 #define PTL2_ENTRIES_ARCH 	0
-
 /* coarse page tables used (256 * 4 = 1KB per page) */
 #define PTL3_ENTRIES_ARCH 	(2 << 8)	/* 256 */
 
+/* Page table sizes for each level. */
 #define PTL0_SIZE_ARCH 		FOUR_FRAMES
 #define PTL1_SIZE_ARCH 		0
@@ -68,4 +69,5 @@
 #define PTL3_SIZE_ARCH 		ONE_FRAME
 
+/* Macros calculating indices into page tables for each level. */
 #define PTL0_INDEX_ARCH(vaddr) 	(((vaddr) >> 20) & 0xfff)
 #define PTL1_INDEX_ARCH(vaddr) 	0
@@ -73,4 +75,5 @@
 #define PTL3_INDEX_ARCH(vaddr) 	(((vaddr) >> 12) & 0x0ff)
 
+/* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
 	((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
@@ -82,4 +85,5 @@
 	((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
 
+/* Set PTE address accessors for each level. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
 	(set_ptl0_addr((pte_level0_t *) (ptl0)))
@@ -91,4 +95,5 @@
 	(((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
 
+/* Get PTE flags accessors for each level. */
 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
 	get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
@@ -100,4 +105,5 @@
 	get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
 
+/* Set PTE flags accessors for each level. */
 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
 	set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
@@ -107,18 +113,14 @@
 	set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
 
+/* Macros for querying the last-level PTE entries. */
 #define PTE_VALID_ARCH(pte) \
 	(*((uint32_t *) (pte)) != 0)
 #define PTE_PRESENT_ARCH(pte) \
 	(((pte_level0_t *) (pte))->descriptor_type != 0)
-
-/* pte should point into ptl3 */
 #define PTE_GET_FRAME_ARCH(pte) \
 	(((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
-
-/* pte should point into ptl3 */
 #define PTE_WRITABLE_ARCH(pte) \
 	(((pte_level1_t *) (pte))->access_permission_0 == \
 	    PTE_AP_USER_RW_KERNEL_RW)
-
 #define PTE_EXECUTABLE_ARCH(pte) \
 	1
@@ -129,8 +131,8 @@
 typedef struct {
 	/* 0b01 for coarse tables, see below for details */
-	unsigned descriptor_type     : 2;
-	unsigned impl_specific       : 3;
-	unsigned domain              : 4;
-	unsigned should_be_zero      : 1;
+	unsigned descriptor_type : 2;
+	unsigned impl_specific : 3;
+	unsigned domain : 4;
+	unsigned should_be_zero : 1;
 
 	/* Pointer to the coarse 2nd level page table (holding entries for small
@@ -139,5 +141,5 @@
 	 * per table in comparison with 1KB per the coarse table)
 	 */
-	unsigned coarse_table_addr   : 22;
+	unsigned coarse_table_addr : 22;
 } ATTRIBUTE_PACKED pte_level0_t;
 
@@ -146,7 +148,7 @@
 
 	/* 0b10 for small pages */
-	unsigned descriptor_type     : 2;
-	unsigned bufferable          : 1;
-	unsigned cacheable           : 1;
+	unsigned descriptor_type : 2;
+	unsigned bufferable : 1;
+	unsigned cacheable : 1;
 
 	/* access permissions for each of 4 subparts of a page
@@ -156,5 +158,5 @@
 	unsigned access_permission_2 : 2;
 	unsigned access_permission_3 : 2;
-	unsigned frame_base_addr     : 20;
+	unsigned frame_base_addr : 20;
 } ATTRIBUTE_PACKED pte_level1_t;
 
@@ -191,5 +193,5 @@
  * @param pt    Pointer to the page table to set.
  */   
-static inline void set_ptl0_addr( pte_level0_t *pt)
+static inline void set_ptl0_addr(pte_level0_t *pt)
 {
 	asm volatile (
Index: kernel/arch/arm32/include/mm/page_fault.h
===================================================================
--- kernel/arch/arm32/include/mm/page_fault.h	(revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe)
+++ kernel/arch/arm32/include/mm/page_fault.h	(revision 8b243f295e54de841c17a2606bdc9a2fe484dbbb)
@@ -42,8 +42,8 @@
 /** Decribes CP15 "fault status register" (FSR). */
 typedef struct {
-	unsigned status           : 3;
-	unsigned domain           : 4;
-	unsigned zero             : 1;
-	unsigned should_be_zero   : 24;
+	unsigned status : 3;
+	unsigned domain : 4;
+	unsigned zero : 1;
+	unsigned should_be_zero : 24;
 } ATTRIBUTE_PACKED fault_status_t;
 
@@ -62,12 +62,12 @@
  */
 typedef struct {
-	unsigned dummy1        : 4;
-	unsigned bit4          : 1;
-	unsigned bits567       : 3;
-	unsigned dummy         : 12;
-	unsigned access        : 1;
-	unsigned opcode        : 4;
-	unsigned type          : 3;
-	unsigned condition     : 4;
+	unsigned dummy1 : 4;
+	unsigned bit4 : 1;
+	unsigned bits567 : 3;
+	unsigned dummy : 12;
+	unsigned access : 1;
+	unsigned opcode : 4;
+	unsigned type : 3;
+	unsigned condition : 4;
 } ATTRIBUTE_PACKED instruction_t;