Index: Makefile.config
===================================================================
--- Makefile.config	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
+++ Makefile.config	(revision 8a0b3730253d37644b2f98837df6a6cf1a716bf8)
@@ -41,6 +41,6 @@
 #CONFIG_TEST = synch/rwlock2
 #CONFIG_TEST = synch/rwlock3
-CONFIG_TEST = synch/rwlock4
-#CONFIG_TEST = synch/rwlock5
+#CONFIG_TEST = synch/rwlock4
+CONFIG_TEST = synch/rwlock5
 #CONFIG_TEST = synch/semaphore1
 #CONFIG_TEST = synch/semaphore2
Index: arch/ia64/include/atomic.h
===================================================================
--- arch/ia64/include/atomic.h	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
+++ arch/ia64/include/atomic.h	(revision 8a0b3730253d37644b2f98837df6a6cf1a716bf8)
@@ -41,6 +41,4 @@
  	__asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (*val) : "i" (imm));
  
- 	*val += imm;
-	
 	return v;
 }
@@ -54,9 +52,6 @@
 
 
-static inline atomic_t atomic_inc_post(atomic_t *val) { return atomic_add(val, 1)+1; }
-static inline atomic_t atomic_dec_post(atomic_t *val) { return atomic_add(val, -1)-1; }
-
-
-
+static inline atomic_t atomic_inc_post(atomic_t *val) { return atomic_add(val, 1) + 1; }
+static inline atomic_t atomic_dec_post(atomic_t *val) { return atomic_add(val, -1) - 1; }
 
 #endif
Index: arch/ia64/src/ivt.S
===================================================================
--- arch/ia64/src/ivt.S	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
+++ arch/ia64/src/ivt.S	(revision 8a0b3730253d37644b2f98837df6a6cf1a716bf8)
@@ -1,4 +1,5 @@
 #
 # Copyright (C) 2005 Jakub Vana
+# Copyright (C) 2005 Jakub Jermar
 # All rights reserved.
 #
@@ -28,4 +29,5 @@
 
 #include <arch/stack.h>
+#include <arch/register.h>
 
 #define STACK_ITEMS		12
@@ -105,5 +107,5 @@
 	
 	/* assume kernel backing store */
-	mov ar.bspstore = r28 ;;
+	/* mov ar.bspstore = r28 ;; */
 	
 	mov r29 = ar.bsp
@@ -145,6 +147,6 @@
 	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
-	mov ar.bspstore = r28 ;;	/* (step 4) */
-	mov ar.rnat = r27		/* (step 5) */
+	/* mov ar.bspstore = r28 ;; */	/* (step 4) */
+	/* mov ar.rnat = r27 */		/* (step 5) */
 
 	mov ar.pfs = r25		/* (step 6) */
@@ -190,5 +192,5 @@
 
     /* 6. switch to bank 1 and reenable PSR.ic */
-	ssm 0x2000
+	ssm PSR_IC_MASK
 	bsw.1 ;;
 	srlz.d
@@ -246,4 +248,9 @@
     
     /* 9. skipped (will not enable interrupts) */
+	/*
+    	 * ssm PSR_I_MASK
+	 * ;;
+	 * srlz.d
+	 */
 
     /* 10. call handler */
@@ -255,4 +262,9 @@
 	
     /* 12. skipped (will not disable interrupts) */
+	/*
+    	 * rsm PSR_I_MASK
+	 * ;;
+	 * srlz.d
+	 */
 
     /* 13. restore general and floating-point registers */
@@ -308,5 +320,5 @@
 	
     /* 15. disable PSR.ic and switch to bank 0 */
-	rsm 0x2000
+	rsm PSR_IC_MASK
 	bsw.0 ;;
 	srlz.d