Index: arch/amd64/Makefile.inc =================================================================== --- arch/amd64/Makefile.inc (revision bc1089a990e7d6d859d96cf4f71e6bc8e2a039ad) +++ arch/amd64/Makefile.inc (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -34,3 +34,4 @@ arch/asm_utils.S \ arch/fmath.c \ - arch/mm/memory_init.c + arch/mm/memory_init.c \ + arch/cpu/cpu.c Index: arch/amd64/include/cpu.h =================================================================== --- arch/amd64/include/cpu.h (revision bc1089a990e7d6d859d96cf4f71e6bc8e2a039ad) +++ arch/amd64/include/cpu.h (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -30,9 +30,16 @@ #define __amd64_CPU_H__ -#include -#include + +#define EFER_MSR_NUM 0xc0000080 +#define AMD_SCE_FLAG 0 +#define AMD_LME_FLAG 8 +#define AMD_LMA_FLAG 10 +#define AMD_FFXSR_FLAG 14 +#define AMD_NXE_FLAG 11 + +#ifndef __ASM__ + #include #include -#include struct cpu_arch { @@ -45,6 +52,10 @@ -void set_TS_flag(void); -void reset_TS_flag(void); +extern void set_TS_flag(void); +extern void reset_TS_flag(void); +extern void set_efer_flag(int flag); +extern __u64 read_efer_flag(void); + +#endif /* __ASM__ */ #endif Index: arch/amd64/include/cpuid.h =================================================================== --- arch/amd64/include/cpuid.h (revision bc1089a990e7d6d859d96cf4f71e6bc8e2a039ad) +++ arch/amd64/include/cpuid.h (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -32,4 +32,7 @@ #include +#define AMD_CPUID_EXTENDED 0x80000001 +#define AMD_EXT_NOEXECUTE 20 + struct cpu_info { __u32 cpuid_eax; @@ -41,18 +44,6 @@ extern int has_cpuid(void); -static inline void cpuid(__u32 cmd, cpu_info_t *info) -{ - __asm__ ( - "movl %1, %eax" - "cpuid" - "movl %eax, 0(%0)" - "movl %ebx, 4(%0)" - "movl %ecx, 8(%0)" - "movl %edx, 12(%0)" - : "=m"(info) - : "r"(cmd) - : "%eax","%ebx","%ecx","%edx" - ); -} +extern void cpuid(__u32 cmd, cpu_info_t *info); + extern __u64 rdtsc(void); Index: arch/amd64/include/mm/page.h =================================================================== --- arch/amd64/include/mm/page.h (revision bc1089a990e7d6d859d96cf4f71e6bc8e2a039ad) +++ arch/amd64/include/mm/page.h (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -43,5 +43,5 @@ #else # define KA2PA(x) ((x) + 0x80000000) -//# define PA2KA(x) ((x)) - 0x80000000) +# define PA2KA(x) ((x) - 0x80000000) #endif Index: arch/amd64/src/amd64.c =================================================================== --- arch/amd64/src/amd64.c (revision bc1089a990e7d6d859d96cf4f71e6bc8e2a039ad) +++ arch/amd64/src/amd64.c (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -40,7 +40,20 @@ #include #include +#include +#include +#include void arch_pre_mm_init(void) { + struct cpu_info cpuid_s; + + cpuid(AMD_CPUID_EXTENDED,&cpuid_s); + if (! (cpuid_s.cpuid_edx & (1< #include +#include #define START_STACK 0x7c00 @@ -102,7 +103,7 @@ # Enable long mode - movl $0xc0000080, %ecx # EFER MSR number + movl $EFER_MSR_NUM, %ecx # EFER MSR number rdmsr # Read EFER - btsl $8, %eax # Set LME=1 + btsl $AMD_LME_FLAG, %eax # Set LME=1 wrmsr # Write EFER Index: arch/amd64/src/cpu/cpu.c =================================================================== --- arch/amd64/src/cpu/cpu.c (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) +++ arch/amd64/src/cpu/cpu.c (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2001-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +/* + * Identification of CPUs. + * Contains only non-MP-Specification specific SMP code. + */ +#define AMD_CPUID_EBX 0x68747541 +#define AMD_CPUID_ECX 0x444d4163 +#define AMD_CPUID_EDX 0x69746e65 + +#define INTEL_CPUID_EBX 0x756e6547 +#define INTEL_CPUID_ECX 0x6c65746e +#define INTEL_CPUID_EDX 0x49656e69 + + +enum vendor { + VendorUnknown=0, + VendorAMD, + VendorIntel +}; + +static char *vendor_str[] = { + "Unknown Vendor", + "AuthenticAMD", + "GenuineIntel" +}; + +void set_TS_flag(void) +{ + asm + ( + "mov %%cr0,%%rax;" + "or $8,%%rax;" + "mov %%rax,%%cr0;" + : + : + :"%rax" + ); +} + +void reset_TS_flag(void) +{ + asm + ( + "mov %%cr0,%%rax;" + "btc $4,%%rax;" + "mov %%rax,%%cr0;" + : + : + :"%rax" + ); +} Index: arch/amd64/src/dummy.s =================================================================== --- arch/amd64/src/dummy.s (revision bc1089a990e7d6d859d96cf4f71e6bc8e2a039ad) +++ arch/amd64/src/dummy.s (revision 89344d856a4700e9b4c9db22b56fee07c4092e0e) @@ -36,5 +36,4 @@ .global cpu_print_report .global dummy -.global reset_TS_flag .global fpu_init @@ -45,5 +44,4 @@ cpu_sleep: cpu_print_report: -reset_TS_flag: fpu_init: