Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 8800b13065d75eefbc778f2b003bc4253f57fc29)
@@ -169,10 +169,10 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-	 /* ICache coherency is elaborated on in barrier.h.
-	  * VIPT and PIPT caches need maintenance only on code modify,
-	  * so it should be safe for general use.
-	  * Enable branch predictors too as they follow the same rules
-	  * as ICache and they can be flushed together
-	  */
+	/* ICache coherency is elaborated on in barrier.h.
+	 * VIPT and PIPT caches need maintenance only on code modify,
+	 * so it should be safe for general use.
+	 * Enable branch predictors too as they follow the same rules
+	 * as ICache and they can be flushed together
+	 */
 	if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
 		control_reg |=