Changeset 8565a42 in mainline for uspace/lib/c/arch/arm32
- Timestamp:
- 2018-03-02T20:34:50Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- a1a81f69, d5e5fd1
- Parents:
- 3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)
- git-committer:
- GitHub <noreply@…> (2018-03-02 20:34:50)
- Location:
- uspace/lib/c/arch/arm32
- Files:
-
- 6 edited
-
_link.ld.in (modified) (5 diffs)
-
include/libarch/atomic.h (modified) (6 diffs)
-
src/entry.S (modified) (2 diffs)
-
src/fibril.S (modified) (2 diffs)
-
src/syscall.c (modified) (2 diffs)
-
src/thread_entry.S (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
uspace/lib/c/arch/arm32/_link.ld.in
r3061bc1 r8565a42 18 18 . = 0x1000 + SIZEOF_HEADERS; 19 19 #endif 20 20 21 21 .init : { 22 22 *(.init); 23 23 } :text 24 24 25 25 .text : { 26 26 *(.text .text.*); 27 27 *(.rodata .rodata.*); 28 28 } :text 29 29 30 30 #ifdef LOADER 31 31 .interp : { … … 33 33 } :interp :text 34 34 #endif 35 35 36 36 . = . + 0x1000; 37 37 38 38 .data : { 39 39 *(.opd); … … 41 41 *(.sdata); 42 42 } :data 43 43 44 44 .tdata : { 45 45 _tdata_start = .; … … 50 50 _tbss_end = .; 51 51 } :data 52 52 53 53 _tls_alignment = ALIGNOF(.tdata); 54 54 55 55 .bss : { 56 56 *(.sbss); … … 59 59 *(.bss); 60 60 } :data 61 61 62 62 /DISCARD/ : { 63 63 *(*); -
uspace/lib/c/arch/arm32/include/libarch/atomic.h
r3061bc1 r8565a42 49 49 { 50 50 atomic_count_t ret = 0; 51 51 52 52 /* 53 53 * The following instructions between labels 1 and 2 constitute a … … 75 75 : "memory" 76 76 ); 77 77 78 78 ras_page[0] = 0; 79 79 asm volatile ( … … 81 81 ); 82 82 ras_page[1] = 0xffffffff; 83 83 84 84 return ret != 0; 85 85 } … … 96 96 { 97 97 atomic_count_t ret = 0; 98 98 99 99 /* 100 100 * The following instructions between labels 1 and 2 constitute a … … 118 118 : [imm] "r" (i) 119 119 ); 120 120 121 121 ras_page[0] = 0; 122 122 asm volatile ( … … 124 124 ); 125 125 ras_page[1] = 0xffffffff; 126 126 127 127 return ret; 128 128 } -
uspace/lib/c/arch/arm32/src/entry.S
r3061bc1 r8565a42 42 42 ldr r0, =ras_page 43 43 str r2, [r0] 44 44 45 45 # 46 46 # Create the first stack frame. … … 50 50 push {fp, ip, lr, pc} 51 51 sub fp, ip, #4 52 52 53 53 # Pass pcb_ptr to __main as the first argument (in r0) 54 54 mov r0, r1 -
uspace/lib/c/arch/arm32/src/fibril.S
r3061bc1 r8565a42 34 34 stmia r0!, {sp, lr} 35 35 stmia r0!, {r4-r11} 36 36 37 37 # return 1 38 38 mov r0, #1 … … 43 43 ldmia r0!, {sp, lr} 44 44 ldmia r0!, {r4-r11} 45 45 46 46 # return 0 47 47 mov r0, #0 -
uspace/lib/c/arch/arm32/src/syscall.c
r3061bc1 r8565a42 60 60 register sysarg_t __arm_reg_r5 asm("r5") = p6; 61 61 register sysarg_t __arm_reg_r6 asm("r6") = id; 62 62 63 63 asm volatile ( 64 64 "swi 0" … … 72 72 "r" (__arm_reg_r6) 73 73 ); 74 74 75 75 return __arm_reg_r0; 76 76 } -
uspace/lib/c/arch/arm32/src/thread_entry.S
r3061bc1 r8565a42 42 42 push {fp, ip, lr, pc} 43 43 sub fp, ip, #4 44 44 45 45 b __thread_main
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