Changeset 8565a42 in mainline for uspace/lib/c/arch/amd64
- Timestamp:
- 2018-03-02T20:34:50Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- a1a81f69, d5e5fd1
- Parents:
- 3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)
- git-committer:
- GitHub <noreply@…> (2018-03-02 20:34:50)
- Location:
- uspace/lib/c/arch/amd64
- Files:
-
- 7 edited
-
_link.ld.in (modified) (4 diffs)
-
include/libarch/atomic.h (modified) (4 diffs)
-
src/entry.S (modified) (1 diff)
-
src/entryjmp.S (modified) (1 diff)
-
src/fibril.S (modified) (3 diffs)
-
src/syscall.S (modified) (1 diff)
-
src/thread_entry.S (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
uspace/lib/c/arch/amd64/_link.ld.in
r3061bc1 r8565a42 19 19 . = 0x1000 + SIZEOF_HEADERS; 20 20 #endif 21 21 22 22 .init : { 23 23 *(.init); 24 24 } :text 25 25 26 26 .text : { 27 27 *(.text .text.*); 28 28 *(.rodata .rodata.*); 29 29 } :text 30 30 31 31 #ifdef LOADER 32 32 .interp : { … … 34 34 } :interp :text 35 35 #endif 36 36 37 37 . = . + 0x1000; 38 38 39 39 .data : { 40 40 *(.data); 41 41 *(.data.rel*); 42 42 } :data 43 43 44 44 .tdata : { 45 45 _tdata_start = .; … … 50 50 _tbss_end = .; 51 51 } :data 52 52 53 53 _tls_alignment = ALIGNOF(.tdata); 54 54 55 55 .bss : { 56 56 *(COMMON); 57 57 *(.bss); 58 58 } :data 59 59 60 60 #ifdef CONFIG_LINE_DEBUG 61 61 .comment 0 : { *(.comment); } :debug … … 70 70 .debug_str 0 : { *(.debug_str); } :debug 71 71 #endif 72 72 73 73 /DISCARD/ : { 74 74 *(*); -
uspace/lib/c/arch/amd64/include/libarch/atomic.h
r3061bc1 r8565a42 75 75 { 76 76 atomic_count_t r = 1; 77 77 78 78 #ifdef __PCC__ 79 79 asm volatile ( … … 89 89 ); 90 90 #endif 91 91 92 92 return r; 93 93 } … … 96 96 { 97 97 atomic_count_t r = -1; 98 98 99 99 #ifdef __PCC__ 100 100 asm volatile ( … … 110 110 ); 111 111 #endif 112 112 113 113 return r; 114 114 } -
uspace/lib/c/arch/amd64/src/entry.S
r3061bc1 r8565a42 44 44 pushq $0 45 45 movq %rsp, %rbp 46 46 47 47 # %rdi was deliberately chosen as the first argument is also in %rdi 48 48 # Pass PCB pointer to __main (no operation) -
uspace/lib/c/arch/amd64/src/entryjmp.S
r3061bc1 r8565a42 39 39 push %rbp 40 40 movq %rsp, %rbp 41 41 42 42 # pcb must be passed in %rdi, use %rdx as a scratch register 43 43 mov %rdi, %rdx 44 44 mov %rsi, %rdi 45 45 46 46 # jump to entry point 47 47 jmp *%rdx -
uspace/lib/c/arch/amd64/src/fibril.S
r3061bc1 r8565a42 39 39 FUNCTION_BEGIN(context_save) 40 40 movq (%rsp), %rdx # the caller's return %eip 41 41 42 42 # in %rdi is passed 1st argument 43 43 movq %rdx, CONTEXT_OFFSET_PC(%rdi) 44 44 movq %rsp, CONTEXT_OFFSET_SP(%rdi) 45 45 46 46 movq %rbx, CONTEXT_OFFSET_RBX(%rdi) 47 47 movq %rbp, CONTEXT_OFFSET_RBP(%rdi) … … 50 50 movq %r14, CONTEXT_OFFSET_R14(%rdi) 51 51 movq %r15, CONTEXT_OFFSET_R15(%rdi) 52 52 53 53 movq %fs:0, %rax 54 54 movq %rax, CONTEXT_OFFSET_TLS(%rdi) 55 55 56 56 xorl %eax, %eax # context_save returns 1 57 57 incl %eax … … 71 71 movq CONTEXT_OFFSET_RBP(%rdi), %rbp 72 72 movq CONTEXT_OFFSET_RBX(%rdi), %rbx 73 73 74 74 movq CONTEXT_OFFSET_SP(%rdi), %rsp # ctx->sp -> %rsp 75 75 76 76 movq CONTEXT_OFFSET_PC(%rdi), %rdx 77 77 78 78 movq %rdx,(%rsp) 79 79 80 80 movq CONTEXT_OFFSET_TLS(%rdi), %rdi 81 81 movq %rdi, %fs:0 82 82 83 83 xorl %eax, %eax # context_restore returns 0 84 84 ret -
uspace/lib/c/arch/amd64/src/syscall.S
r3061bc1 r8565a42 30 30 31 31 .text 32 32 33 33 ## Make a system call. 34 34 # -
uspace/lib/c/arch/amd64/src/thread_entry.S
r3061bc1 r8565a42 41 41 pushq $0 42 42 movq %rsp, %rbp 43 43 44 44 # 45 45 # RAX contains address of uarg
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