Index: kernel/arch/amd64/include/arch/asm.h
===================================================================
--- kernel/arch/amd64/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/amd64/include/arch/asm.h	(revision 8565a42398543d14e36b2df6f7a70c6237b458f8)
@@ -53,5 +53,5 @@
 {
 	uintptr_t v;
-	
+
 	asm volatile (
 		"andq %%rsp, %[v]\n"
@@ -59,5 +59,5 @@
 		: "0" (~((uint64_t) STACK_SIZE - 1))
 	);
-	
+
 	return v;
 }
@@ -91,5 +91,5 @@
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
 		uint8_t val;
-		
+
 		asm volatile (
 			"inb %w[port], %b[val]\n"
@@ -97,5 +97,5 @@
 			: [port] "d" (port)
 		);
-		
+
 		return val;
 	} else
@@ -115,5 +115,5 @@
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
 		uint16_t val;
-		
+
 		asm volatile (
 			"inw %w[port], %w[val]\n"
@@ -121,5 +121,5 @@
 			: [port] "d" (port)
 		);
-		
+
 		return val;
 	} else
@@ -139,5 +139,5 @@
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
 		uint32_t val;
-		
+
 		asm volatile (
 			"inl %w[port], %[val]\n"
@@ -145,5 +145,5 @@
 			: [port] "d" (port)
 		);
-		
+
 		return val;
 	} else
@@ -252,7 +252,7 @@
 {
 	ipl_t ipl = interrupts_read();
-	
+
 	asm volatile ("sti\n");
-	
+
 	return ipl;
 }
@@ -268,7 +268,7 @@
 {
 	ipl_t ipl = interrupts_read();
-	
+
 	asm volatile ("cli\n");
-	
+
 	return ipl;
 }
@@ -310,5 +310,5 @@
 {
 	uint32_t ax, dx;
-	
+
 	asm volatile (
 		"rdmsr\n"
@@ -316,5 +316,5 @@
 		: "c" (msr)
 	);
-	
+
 	return ((uint64_t) dx << 32) | ax;
 }
Index: kernel/arch/amd64/include/arch/atomic.h
===================================================================
--- kernel/arch/amd64/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/amd64/include/arch/atomic.h	(revision 8565a42398543d14e36b2df6f7a70c6237b458f8)
@@ -74,5 +74,5 @@
 {
 	atomic_count_t r = 1;
-	
+
 	asm volatile (
 		"lock xaddq %[r], %[count]\n"
@@ -80,5 +80,5 @@
 		  [r] "+r" (r)
 	);
-	
+
 	return r;
 }
@@ -87,5 +87,5 @@
 {
 	atomic_count_t r = -1;
-	
+
 	asm volatile (
 		"lock xaddq %[r], %[count]\n"
@@ -93,5 +93,5 @@
 		  [r] "+r" (r)
 	);
-	
+
 	return r;
 }
@@ -103,5 +103,5 @@
 {
 	atomic_count_t v = 1;
-	
+
 	asm volatile (
 		"xchgq %[v], %[count]\n"
@@ -109,5 +109,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return v;
 }
@@ -117,5 +117,5 @@
 {
 	atomic_count_t tmp;
-	
+
 	preemption_disable();
 	asm volatile (
@@ -125,5 +125,5 @@
 		"	testq %[tmp], %[tmp]\n"
 		"	jnz 0b\n"       /* lightweight looping on locked spinlock */
-		
+
 		"	incq %[tmp]\n"  /* now use the atomic operation */
 		"	xchgq %[count], %[tmp]\n"
@@ -133,5 +133,5 @@
 		  [tmp] "=&r" (tmp)
 	);
-	
+
 	/*
 	 * Prevent critical section code from bleeding out this way up.
Index: kernel/arch/amd64/include/arch/cpu.h
===================================================================
--- kernel/arch/amd64/include/arch/cpu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/amd64/include/arch/cpu.h	(revision 8565a42398543d14e36b2df6f7a70c6237b458f8)
@@ -89,7 +89,7 @@
 	int stepping;
 	tss_t *tss;
-	
+
 	unsigned int id; /** CPU's local, ie physical, APIC ID. */
-	
+
 	size_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
 } cpu_arch_t;
Index: kernel/arch/amd64/include/arch/cycle.h
===================================================================
--- kernel/arch/amd64/include/arch/cycle.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/amd64/include/arch/cycle.h	(revision 8565a42398543d14e36b2df6f7a70c6237b458f8)
@@ -42,5 +42,5 @@
 	uint32_t lower;
 	uint32_t upper;
-	
+
 	asm volatile (
 		"rdtsc\n"
@@ -48,5 +48,5 @@
 		  "=d" (upper)
 	);
-	
+
 	return ((uint64_t) lower) | (((uint64_t) upper) << 32);
 }
Index: kernel/arch/amd64/include/arch/mm/page.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/amd64/include/arch/mm/page.h	(revision 8565a42398543d14e36b2df6f7a70c6237b458f8)
@@ -210,5 +210,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
 	    (!p->present) << PAGE_PRESENT_SHIFT |
@@ -223,5 +223,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
 	p->addr_32_51 = a >> 32;
@@ -231,5 +231,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	p->page_cache_disable = !(flags & PAGE_CACHEABLE);
 	p->present = !(flags & PAGE_NOT_PRESENT);
@@ -238,5 +238,5 @@
 	p->no_execute = (flags & PAGE_EXEC) == 0;
 	p->global = (flags & PAGE_GLOBAL) != 0;
-	
+
 	/*
 	 * Ensure that there is at least one bit set even if the present bit is cleared.