Index: kernel/arch/arm32/include/arch.h =================================================================== --- kernel/arch/arm32/include/arch.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,62 +1,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Empty. - */ - -#ifndef KERN_arm32_ARCH_H_ -#define KERN_arm32_ARCH_H_ - -#define TASKMAP_MAX_RECORDS 32 -#define CPUMAP_MAX_RECORDS 32 - -#define BOOTINFO_TASK_NAME_BUFLEN 32 - -#include - -typedef struct { - void *addr; - size_t size; - char name[BOOTINFO_TASK_NAME_BUFLEN]; -} utask_t; - -typedef struct { - size_t cnt; - utask_t tasks[TASKMAP_MAX_RECORDS]; -} bootinfo_t; - -extern void arch_pre_main(void *entry, bootinfo_t *bootinfo); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/arch/arch.h =================================================================== --- kernel/arch/arm32/include/arch/arch.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/arch.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Empty. + */ + +#ifndef KERN_arm32_ARCH_H_ +#define KERN_arm32_ARCH_H_ + +#define TASKMAP_MAX_RECORDS 32 +#define CPUMAP_MAX_RECORDS 32 + +#define BOOTINFO_TASK_NAME_BUFLEN 32 + +#include + +typedef struct { + void *addr; + size_t size; + char name[BOOTINFO_TASK_NAME_BUFLEN]; +} utask_t; + +typedef struct { + size_t cnt; + utask_t tasks[TASKMAP_MAX_RECORDS]; +} bootinfo_t; + +extern void arch_pre_main(void *entry, bootinfo_t *bootinfo); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/asm.h =================================================================== --- kernel/arch/arm32/include/arch/asm.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/asm.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Declarations of functions implemented in assembly. + */ + +#ifndef KERN_arm32_ASM_H_ +#define KERN_arm32_ASM_H_ + +#include +#include +#include +#include +#include + +/** CPU specific way to sleep cpu. + * + * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi). + * ARM920T has custom coprocessor action to do the same. See ARM920T Technical + * Reference Manual ch 4.9 p. 4-23 (103 in the PDF) + * ARM926EJ-S uses the same coprocessor instruction as ARM920T. See ARM926EJ-S + * chapter 2.3.8 p.2-22 (52 in the PDF) + * + * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture + * reference manual for armv4/5 CP15 implementation is mandatory only for + * armv6+. + */ +NO_TRACE static inline void cpu_sleep(void) +{ +#ifdef PROCESSOR_ARCH_armv7_a + asm volatile ( "wfe" ); +#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t) + asm volatile ( "mcr p15, 0, R0, c7, c0, 4" ); +#endif +} + +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) +{ + *port = v; +} + +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) +{ + *port = v; +} + +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) +{ + *port = v; +} + +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) +{ + return *port; +} + +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) +{ + return *port; +} + +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) +{ + return *port; +} + +/** Return base address of current stack. + * + * Return the base address of the current stack. + * The stack is assumed to be STACK_SIZE bytes long. + * The stack must start on page boundary. + * + */ +NO_TRACE static inline uintptr_t get_stack_base(void) +{ + uintptr_t v; + + asm volatile ( + "and %[v], sp, %[size]\n" + : [v] "=r" (v) + : [size] "r" (~(STACK_SIZE - 1)) + ); + + return v; +} + +extern void cpu_halt(void) __attribute__((noreturn)); +extern void asm_delay_loop(uint32_t t); +extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, + uintptr_t entry); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/asm/boot.h =================================================================== --- kernel/arch/arm32/include/arch/asm/boot.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/asm/boot.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Initial kernel start. + */ + +#ifndef KERN_arm32_ASM_BOOT_H_ +#define KERN_arm32_ASM_BOOT_H_ + +/** Size of a temporary stack used for initial kernel start. */ +#define TEMP_STACK_SIZE 0x100 + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/atomic.h =================================================================== --- kernel/arch/arm32/include/arch/atomic.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/atomic.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Atomic operations. + */ + +#ifndef KERN_arm32_ATOMIC_H_ +#define KERN_arm32_ATOMIC_H_ + +#include +#include + +/** Atomic addition. + * + * @param val Where to add. + * @param i Value to be added. + * + * @return Value after addition. + * + */ +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) +{ + /* + * This implementation is for UP pre-ARMv6 systems where we do not have + * the LDREX and STREX instructions. + */ + ipl_t ipl = interrupts_disable(); + val->count += i; + atomic_count_t ret = val->count; + interrupts_restore(ipl); + + return ret; +} + +/** Atomic increment. + * + * @param val Variable to be incremented. + * + */ +NO_TRACE static inline void atomic_inc(atomic_t *val) +{ + atomic_add(val, 1); +} + +/** Atomic decrement. + * + * @param val Variable to be decremented. + * + */ +NO_TRACE static inline void atomic_dec(atomic_t *val) { + atomic_add(val, -1); +} + +/** Atomic pre-increment. + * + * @param val Variable to be incremented. + * @return Value after incrementation. + * + */ +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) +{ + return atomic_add(val, 1); +} + +/** Atomic pre-decrement. + * + * @param val Variable to be decremented. + * @return Value after decrementation. + * + */ +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) +{ + return atomic_add(val, -1); +} + +/** Atomic post-increment. + * + * @param val Variable to be incremented. + * @return Value before incrementation. + * + */ +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) +{ + return atomic_add(val, 1) - 1; +} + +/** Atomic post-decrement. + * + * @param val Variable to be decremented. + * @return Value before decrementation. + * + */ +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) +{ + return atomic_add(val, -1) + 1; +} + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/barrier.h =================================================================== --- kernel/arch/arm32/include/arch/barrier.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/barrier.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Memory barriers. + */ + +#ifndef KERN_arm32_BARRIER_H_ +#define KERN_arm32_BARRIER_H_ + +#ifdef KERNEL +#include +#else +#include +#endif + +#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") +#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") + +#if defined PROCESSOR_ARCH_armv7_a +/* ARMv7 uses instructions for memory barriers see ARM Architecture reference + * manual for details: + * DMB: ch. A8.8.43 page A8-376 + * DSB: ch. A8.8.44 page A8-378 + * See ch. A3.8.3 page A3-148 for details about memory barrier implementation + * and functionality on armv7 architecture. + */ +#define memory_barrier() asm volatile ("dmb" ::: "memory") +#define read_barrier() asm volatile ("dsb" ::: "memory") +#define write_barrier() asm volatile ("dsb st" ::: "memory") +#define inst_barrier() asm volatile ("isb" ::: "memory") +#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL +/* + * ARMv6 introduced user access of the following commands: + * - Prefetch flush + * - Data synchronization barrier + * - Data memory barrier + * - Clean and prefetch range operations. + * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4 + */ +/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions. + * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs, + * CP15 implementation is mandatory only for armv6+. + */ +#define memory_barrier() CP15DMB_write(0) +#define read_barrier() CP15DSB_write(0) +#define write_barrier() read_barrier() +#define inst_barrier() CP15ISB_write(0) +#else +/* Older manuals mention syscalls as a way to implement cache coherency and + * barriers. See for example ARM Architecture Reference Manual Version D + * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28) + */ +// TODO implement on per PROCESSOR basis or via syscalls +#define memory_barrier() asm volatile ("" ::: "memory") +#define read_barrier() asm volatile ("" ::: "memory") +#define write_barrier() asm volatile ("" ::: "memory") +#define inst_barrier() asm volatile ("" ::: "memory") +#endif + +/* + * There are multiple ways ICache can be implemented on ARM machines. Namely + * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference + * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum + * compatibility across processors, ARM recommends that operating systems target + * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, + * and do not assume the presence of the IVIPT extension. Software that relies + * on the IVIPT extension might fail in an unpredictable way on an ARMv7 + * implementation that does not include the IVIPT extension." (7.2.6 p. 245). + * Only PIPT invalidates cache for all VA aliases if one block is invalidated. + * + * @note: Supporting ASID and VMID tagged VIVT may need to add ICache + * maintenance to other places than just smc. + */ + +#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL +/* Available on all supported arms, + * invalidates entire ICache so the written value does not matter. */ +//TODO might be PL1 only on armv5- +#define smc_coherence(a) \ +do { \ + DCCMVAU_write((uint32_t)(a)); /* Flush changed memory */\ + write_barrier(); /* Wait for completion */\ + ICIALLU_write(0); /* Flush ICache */\ + inst_barrier(); /* Wait for Inst refetch */\ +} while (0) +/* @note: Cache type register is not available in uspace. We would need + * to export the cache line value, or use syscall for uspace smc_coherence */ +#define smc_coherence_block(a, l) \ +do { \ + for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\ + smc_coherence(addr); \ +} while (0) +#else +#define smc_coherence(a) +#define smc_coherence_block(a, l) +#endif + + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/cache.h =================================================================== --- kernel/arch/arm32/include/arch/cache.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/cache.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Security Extensions Routines + */ + +#ifndef KERN_arm32_CACHE_H_ +#define KERN_arm32_CACHE_H_ + +unsigned dcache_levels(void); + +void dcache_flush(void); +void dcache_flush_invalidate(void); +void cpu_dcache_flush(void); +void cpu_dcache_flush_invalidate(void); +void icache_invalidate(void); + +#endif +/** @} + */ + Index: kernel/arch/arm32/include/arch/context.h =================================================================== --- kernel/arch/arm32/include/arch/context.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/context.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Thread context. + */ + +#ifndef KERN_arm32_CONTEXT_H_ +#define KERN_arm32_CONTEXT_H_ + +#include +#include + +/* Put one item onto the stack to support get_stack_base() and align it up. */ +#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) + +#define context_set(c, _pc, stack, size) \ + do { \ + (c)->pc = (uintptr_t) (_pc); \ + (c)->sp = ((uintptr_t) (stack)) + (size) - SP_DELTA; \ + (c)->fp = 0; \ + } while (0) + +#ifndef __ASM__ + +#include + +/** Thread context containing registers that must be preserved across function + * calls. + */ +typedef struct { + uint32_t cpu_mode; + uintptr_t sp; + uintptr_t pc; + + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t fp; /* r11 */ + + ipl_t ipl; +} context_t; + + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/cp15.h =================================================================== --- kernel/arch/arm32/include/arch/cp15.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/cp15.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief System Control Coprocessor (CP15) + */ + +#ifndef KERN_arm32_CP15_H_ +#define KERN_arm32_CP15_H_ + + +/** See ARM Architecture reference manual ch. B3.17.1 page B3-1456 + * for the list */ + +#define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \ +static inline uint32_t name##_read() \ +{ \ + uint32_t val; \ + asm volatile ( "mrc p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" : "=r" (val) ); \ + return val; \ +} +#define CONTROL_REG_GEN_WRITE(name, crn, opc1, crm, opc2) \ +static inline void name##_write(uint32_t val) \ +{ \ + asm volatile ( "mcr p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" :: "r" (val) ); \ +} + +/* Identification registers */ +enum { + MIDR_IMPLEMENTER_MASK = 0xff, + MIDR_IMPLEMENTER_SHIFT = 24, + MIDR_VARIANT_MASK = 0xf, + MIDR_VARIANT_SHIFT = 20, + MIDR_ARCHITECTURE_MASK = 0xf, + MIDR_ARCHITECTURE_SHIFT = 16, + MIDR_PART_NUMBER_MASK = 0xfff, + MIDR_PART_NUMBER_SHIFT = 4, + MIDR_REVISION_MASK = 0xf, + MIDR_REVISION_SHIFT = 0, +}; +CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0); + +enum { + CTR_FORMAT_MASK = 0xe0000000, + CTR_FORMAT_ARMv7 = 0x80000000, + CTR_FORMAT_ARMv6 = 0x00000000, + /* ARMv7 format */ + CTR_CWG_MASK = 0xf, + CTR_CWG_SHIFT = 24, + CTR_ERG_MASK = 0xf, + CTR_ERG_SHIFT = 20, + CTR_D_MIN_LINE_MASK = 0xf, + CTR_D_MIN_LINE_SHIFT = 16, + CTR_I_MIN_LINE_MASK = 0xf, + CTR_I_MIN_LINE_SHIFT = 0, + CTR_L1I_POLICY_MASK = 0x0000c000, + CTR_L1I_POLICY_AIVIVT = 0x00004000, + CTR_L1I_POLICY_VIPT = 0x00008000, + CTR_L1I_POLICY_PIPT = 0x0000c000, + /* ARMv6 format */ + CTR_CTYPE_MASK = 0x1e000000, + CTR_CTYPE_WT = 0x00000000, + CTR_CTYPE_WB_NL = 0x04000000, + CTR_CTYPE_WB_D = 0x0a000000, + CTR_CTYPE_WB_A = 0x0c000000, /**< ARMv5- only */ + CTR_CTYPE_WB_B = 0x0e000000, /**< ARMv5- only */ + CTR_CTYPE_WB_C = 0x1c000000, + CTR_SEP_FLAG = 1 << 24, + CTR_DCACHE_P_FLAG = 1 << 23, + CTR_DCACHE_SIZE_MASK = 0xf, + CTR_DCACHE_SIZE_SHIFT = 18, + CTR_DCACHE_ASSOC_MASK = 0x7, + CTR_DCACHE_ASSOC_SHIFT = 15, + CTR_DCACHE_M_FLAG = 1 << 14, + CTR_DCACHE_LEN_MASK = 0x3, + CTR_DCACHE_LEN_SHIFT = 0, + CTR_ICACHE_P_FLAG = 1 << 11, + CTR_ICACHE_SIZE_MASK = 0xf, + CTR_ICACHE_SIZE_SHIFT = 6, + CTR_ICACHE_ASSOC_MASK = 0x7, + CTR_ICACHE_ASSOC_SHIFT = 3, + CTR_ICACHE_M_FLAG = 1 << 2, + CTR_ICACHE_LEN_MASK = 0x3, + CTR_ICACHE_LEN_SHIFT = 0, +}; +CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1); +CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2); +CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3); +CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5); +CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6); + +enum { + ID_PFR0_THUMBEE_MASK = 0xf << 12, + ID_PFR0_THUMBEE = 0x1 << 12, + ID_PFR0_JAZELLE_MASK = 0xf << 8, + ID_PFR0_JAZELLE = 0x1 << 8, + ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8, + ID_PFR0_THUMB_MASK = 0xf << 4, + ID_PFR0_THUMB = 0x1 << 4, + ID_PFR0_THUMB2 = 0x3 << 4, + ID_PFR0_ARM_MASK = 0xf << 0, + ID_PFR0_ARM = 0x1 << 0, +}; +CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0); + +enum { + ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16, + ID_PFR1_GEN_TIMER_EXT = 0x1 << 16, + ID_PFR1_VIRT_EXT_MASK = 0xf << 12, + ID_PFR1_VIRT_EXT = 0x1 << 12, + ID_PFR1_M_PROF_MASK = 0xf << 8, + ID_PFR1_M_PROF_MODEL = 0x2 << 8, + ID_PFR1_SEC_EXT_MASK = 0xf << 4, + ID_PFR1_SEC_EXT = 0x1 << 4, + ID_PFR1_SEC_EXT_RFR = 0x2 << 4, + ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0, + ID_PFR1_ARMV4_MODEL = 0x1 << 0, +}; +CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1); +CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2); +CONTROL_REG_GEN_READ(ID_AFR0, c0, 0, c1, 3); +CONTROL_REG_GEN_READ(ID_MMFR0, c0, 0, c1, 4); +CONTROL_REG_GEN_READ(ID_MMFR1, c0, 0, c1, 5); +CONTROL_REG_GEN_READ(ID_MMFR2, c0, 0, c1, 6); +CONTROL_REG_GEN_READ(ID_MMFR3, c0, 0, c1, 7); + +CONTROL_REG_GEN_READ(ID_ISAR0, c0, 0, c2, 0); +CONTROL_REG_GEN_READ(ID_ISAR1, c0, 0, c2, 1); +CONTROL_REG_GEN_READ(ID_ISAR2, c0, 0, c2, 2); +CONTROL_REG_GEN_READ(ID_ISAR3, c0, 0, c2, 3); +CONTROL_REG_GEN_READ(ID_ISAR4, c0, 0, c2, 4); +CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5); + +enum { + CCSIDR_WT_FLAG = 1 << 31, + CCSIDR_WB_FLAG = 1 << 30, + CCSIDR_RA_FLAG = 1 << 29, + CCSIDR_WA_FLAG = 1 << 28, + CCSIDR_NUMSETS_MASK = 0x7fff, + CCSIDR_NUMSETS_SHIFT = 13, + CCSIDR_ASSOC_MASK = 0x3ff, + CCSIDR_ASSOC_SHIFT = 3, + CCSIDR_LINESIZE_MASK = 0x7, + CCSIDR_LINESIZE_SHIFT = 0, +}; +CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0); + +enum { + CLIDR_LOUU_MASK = 0x7, + CLIDR_LOUU_SHIFT = 27, + CLIDR_LOC_MASK = 0x7, + CLIDR_LOC_SHIFT = 24, + CLIDR_LOUIS_MASK = 0x7, + CLIDR_LOUIS_SHIFT = 21, + CLIDR_NOCACHE = 0x0, + CLIDR_ICACHE_ONLY = 0x1, + CLIDR_DCACHE_ONLY = 0x2, + CLIDR_SEP_CACHE = 0x3, + CLIDR_UNI_CACHE = 0x4, + CLIDR_CACHE_MASK = 0x7, +#define CLIDR_CACHE(level, val) ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK) +}; +CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1); +CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */ + +enum { + CCSELR_LEVEL_MASK = 0x7, + CCSELR_LEVEL_SHIFT = 1, + CCSELR_INSTRUCTION_FLAG = 1 << 0, +}; +CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0); +CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0); +CONTROL_REG_GEN_READ(VPIDR, c0, 4, c0, 0); +CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0); +CONTROL_REG_GEN_READ(VMPIDR, c0, 4, c0, 5); +CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5); + +/* System control registers */ +/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference + * Manual ARMv7-A and ARMv7-R edition, page 1687 */ +enum { + SCTLR_MMU_EN_FLAG = 1 << 0, + SCTLR_ALIGN_CHECK_EN_FLAG = 1 << 1, /* Allow alignemnt check */ + SCTLR_CACHE_EN_FLAG = 1 << 2, + SCTLR_CP15_BARRIER_EN_FLAG = 1 << 5, + SCTLR_B_EN_FLAG = 1 << 7, /* ARMv6-, big endian switch */ + SCTLR_SWAP_EN_FLAG = 1 << 10, + SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11, + SCTLR_INST_CACHE_EN_FLAG = 1 << 12, + SCTLR_HIGH_VECTORS_EN_FLAG = 1 << 13, + SCTLR_ROUND_ROBIN_EN_FLAG = 1 << 14, + SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17, + SCTLR_WRITE_XN_EN_FLAG = 1 << 19, /* Only if virt. supported */ + SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */ + SCTLR_FAST_IRQ_EN_FLAG = 1 << 21, /* Disable impl. specific feat*/ + SCTLR_UNALIGNED_EN_FLAG = 1 << 22, /* Must be 1 on armv7 */ + SCTLR_IRQ_VECTORS_EN_FLAG = 1 << 24, + SCTLR_BIG_ENDIAN_EXC_FLAG = 1 << 25, + SCTLR_NMFI_EN_FLAG = 1 << 27, + SCTLR_TEX_REMAP_EN_FLAG = 1 << 28, + SCTLR_ACCESS_FLAG_EN_FLAG = 1 << 29, + SCTLR_THUMB_EXC_EN_FLAG = 1 << 30, +}; +CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0); +CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0); +CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1); +CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1); + +enum { + CPACR_ASEDIS_FLAG = 1 << 31, + CPACR_D32DIS_FLAG = 1 << 30, + CPACR_TRCDIS_FLAG = 1 << 28, +#define CPACR_CP_MASK(cp) (0x3 << (cp * 2)) +#define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2)) +#define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2)) +#define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2)) +}; +CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2); +CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2); + +/* Implemented as part of Security extensions */ +enum { + SCR_SIF_FLAG = 1 << 9, + SCR_HCE_FLAG = 1 << 8, + SCR_SCD_FLAG = 1 << 7, + SCR_nET_FLAG = 1 << 6, + SCR_AW_FLAG = 1 << 5, + SCR_FW_FLAG = 1 << 4, + SCR_EA_FLAG = 1 << 3, + SCR_FIQ_FLAG = 1 << 2, + SCR_IRQ_FLAG = 1 << 1, + SCR_NS_FLAG = 1 << 0, +}; +CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0); +CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0); +CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1); +CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1); + +enum { + NSACR_NSTRCDIS_FLAG = 1 << 20, + NSACR_RFR_FLAG = 1 << 19, + NSACR_NSASEDIS = 1 << 15, + NSACR_NSD32DIS = 1 << 14, +#define NSACR_CP_FLAG(cp) (1 << cp) +}; +CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2); +CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2); + +/* Implemented as part of Virtualization extensions */ +CONTROL_REG_GEN_READ(HSCTLR, c1, 4, c0, 0); +CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0); +CONTROL_REG_GEN_READ(HACTLR, c1, 4, c0, 1); +CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1); + +CONTROL_REG_GEN_READ(HCR, c1, 4, c1, 0); +CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0); +CONTROL_REG_GEN_READ(HDCR, c1, 4, c1, 1); +CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1); +CONTROL_REG_GEN_READ(HCPTR, c1, 4, c1, 2); +CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2); +CONTROL_REG_GEN_READ(HSTR, c1, 4, c1, 3); +CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3); +CONTROL_REG_GEN_READ(HACR, c1, 4, c1, 7); +CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7); + +/* Memory protection and control registers */ +CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0); +CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0); +CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1); +CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1); +CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2); +CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2); + +CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2); +CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2); +CONTROL_REG_GEN_READ(VTCR, c2, 4, c1, 2); +CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2); + +/* PAE */ +CONTROL_REG_GEN_READ(TTBR0H, c2, 0, c2, 0); +CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0); +CONTROL_REG_GEN_READ(TTBR1H, c2, 0, c2, 1); +CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1); +CONTROL_REG_GEN_READ(HTTBRH, c2, 0, c2, 4); +CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4); +CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6); +CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6); + +CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0); +CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0); + +/* Memory system fault registers */ +CONTROL_REG_GEN_READ(DFSR, c5, 0, c0, 0); +CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0); +CONTROL_REG_GEN_READ(IFSR, c5, 0, c0, 1); +CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1); + +CONTROL_REG_GEN_READ(ADFSR, c5, 0, c1, 0); +CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0); +CONTROL_REG_GEN_READ(AIFSR, c5, 0, c1, 1); +CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1); + +CONTROL_REG_GEN_READ(HADFSR, c5, 4, c1, 0); +CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0); +CONTROL_REG_GEN_READ(HAIFSR, c5, 4, c1, 1); +CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1); +CONTROL_REG_GEN_READ(HSR, c5, 4, c2, 0); +CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0); + +CONTROL_REG_GEN_READ(DFAR, c6, 0, c0, 0); +CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0); +CONTROL_REG_GEN_READ(IFAR, c6, 0, c0, 2); +CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2); + +CONTROL_REG_GEN_READ(HDFAR, c6, 4, c0, 0); +CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0); +CONTROL_REG_GEN_READ(HIFAR, c6, 4, c0, 2); +CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2); +CONTROL_REG_GEN_READ(HPFAR, c6, 4, c0, 4); +CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4); + +/* Cache maintenance, address translation and other */ +CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */ +CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0); +CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6); +CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0); +CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); +CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */ +CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */ +CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0); +CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1); +CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4); +CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6); +CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7); + +CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1); +CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2); + +CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); +CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); +CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); +CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); +CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4); +CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5); +CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6); +CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7); + + +CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1); +CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2); +CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4); +CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5); +CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1); + +CONTROL_REG_GEN_WRITE(PFI, c7, 0, c11, 1); /* armv6 only */ + +CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1); +CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2); + +CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); +CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); + +/* TLB maintenance */ +CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */ +CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */ +CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */ +CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */ + +CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0); +CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1); +CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2); + +CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0); +CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1); +CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2); + +CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0); +CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1); +CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2); +CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3); + +CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */ +CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */ +CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */ + +CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0); +CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1); +CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4); + +/* c9 are performance monitoring resgisters */ +enum { + PMCR_IMP_MASK = 0xff, + PMCR_IMP_SHIFT = 24, + PMCR_IDCODE_MASK = 0xff, + PMCR_IDCODE_SHIFT = 16, + PMCR_EVENT_NUM_MASK = 0x1f, + PMCR_EVENT_NUM_SHIFT = 11, + PMCR_DP_FLAG = 1 << 5, + PMCR_X_FLAG = 1 << 4, + PMCR_D_FLAG = 1 << 3, + PMCR_C_FLAG = 1 << 2, + PMCR_P_FLAG = 1 << 1, + PMCR_E_FLAG = 1 << 0, +}; +CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0); +CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0); +enum { + PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31, +#define PMCNTENSET_COUNTER_EN_FLAG(c) (1 << c) +}; +CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1); +CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1); +CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0); +CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0); + + +/*c10 has tons of reserved too */ +CONTROL_REG_GEN_READ(PRRR, c10, 0, c2, 0); /* no PAE */ +CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */ +CONTROL_REG_GEN_READ(MAIR0, c10, 0, c2, 0); /* PAE */ +CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */ +CONTROL_REG_GEN_READ(NMRR, c10, 0, c2, 1); /* no PAE */ +CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */ +CONTROL_REG_GEN_READ(MAIR1, c10, 0, c2, 1); /* PAE */ +CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */ + +CONTROL_REG_GEN_READ(AMAIR0, c10, 0, c3, 0); /* PAE */ +CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */ +CONTROL_REG_GEN_READ(AMAIR1, c10, 0, c3, 1); /* PAE */ +CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */ + +CONTROL_REG_GEN_READ(HMAIR0, c10, 4, c2, 0); +CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0); +CONTROL_REG_GEN_READ(HMAIR1, c10, 4, c2, 1); +CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1); + +CONTROL_REG_GEN_READ(HAMAIR0, c10, 4, c3, 0); +CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0); +CONTROL_REG_GEN_READ(HAMAIR1, c10, 4, c3, 1); +CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1); + +/* c11 is reserved for TCM and DMA */ + +/* Security extensions */ +CONTROL_REG_GEN_READ(VBAR, c12, 0, c0, 0); +CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0); +CONTROL_REG_GEN_READ(MVBAR, c12, 0, c0, 1); +CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1); + +CONTROL_REG_GEN_READ(ISR, c12, 0, c1, 0); + +CONTROL_REG_GEN_READ(HVBAR, c12, 4, c0, 0); +CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0); + +/* Process context and thread id (FCSE) */ +CONTROL_REG_GEN_READ(FCSEIDR, c13, 0, c0, 0); + +CONTROL_REG_GEN_READ(CONTEXTIDR, c13, 0, c0, 1); +CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1); +CONTROL_REG_GEN_READ(TPIDRURW, c13, 0, c0, 2); +CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2); +CONTROL_REG_GEN_READ(TPIDRURO, c13, 0, c0, 3); +CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3); +CONTROL_REG_GEN_READ(TPIDRPRW, c13, 0, c0, 4); +CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4); + +CONTROL_REG_GEN_READ(HTPIDR, c13, 4, c0, 2); +CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2); + +/* Generic Timer Extensions */ +CONTROL_REG_GEN_READ(CNTFRQ, c14, 0, c0, 0); +CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0); +CONTROL_REG_GEN_READ(CNTKCTL, c14, 0, c1, 0); +CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0); + +CONTROL_REG_GEN_READ(CNTP_TVAL, c14, 0, c2, 0); +CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0); +CONTROL_REG_GEN_READ(CNTP_CTL, c14, 0, c2, 1); +CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1); + +CONTROL_REG_GEN_READ(CNTV_TVAL, c14, 0, c3, 0); +CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0); +CONTROL_REG_GEN_READ(CNTV_CTL, c14, 0, c3, 1); +CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1); + +CONTROL_REG_GEN_READ(CNTHCTL, c14, 4, c1, 0); +CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0); + +CONTROL_REG_GEN_READ(CNTHP_TVAL, c14, 4, c2, 0); +CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0); +CONTROL_REG_GEN_READ(CNTHP_CTL, c14, 4, c2, 1); +CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/cpu.h =================================================================== --- kernel/arch/arm32/include/arch/cpu.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/cpu.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief CPU identification. + */ + +#ifndef KERN_arm32_CPU_H_ +#define KERN_arm32_CPU_H_ + +#include +#include + +enum { + ARM_MAX_CACHE_LEVELS = 7, +}; + +/** Struct representing ARM CPU identification. */ +typedef struct { + /** Implementor (vendor) number. */ + uint32_t imp_num; + + /** Variant number. */ + uint32_t variant_num; + + /** Architecture number. */ + uint32_t arch_num; + + /** Primary part number. */ + uint32_t prim_part_num; + + /** Revision number. */ + uint32_t rev_num; + + struct { + unsigned ways; + unsigned sets; + unsigned line_size; + unsigned way_shift; + unsigned set_shift; + } dcache[ARM_MAX_CACHE_LEVELS]; + unsigned dcache_levels; +} cpu_arch_t; + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/cycle.h =================================================================== --- kernel/arch/arm32/include/arch/cycle.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/cycle.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Count of CPU cycles. + */ + +#ifndef KERN_arm32_CYCLE_H_ +#define KERN_arm32_CYCLE_H_ + +#include +#include + +/** Return count of CPU cycles. + * + * No such instruction on ARM to get count of cycles. + * + * @return Count of CPU cycles. + * + */ +NO_TRACE static inline uint64_t get_cycle(void) +{ +#ifdef PROCESSOR_ARCH_armv7_a + if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) == + ID_PFR1_GEN_TIMER_EXT) { + uint32_t low = 0, high = 0; + asm volatile( "MRRC p15, 0, %[low], %[high], c14": [low]"=r"(low), [high]"=r"(high)); + return ((uint64_t)high << 32) | low; + } else { + return (uint64_t)PMCCNTR_read() * 64; + } +#endif + return 0; +} + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/elf.h =================================================================== --- kernel/arch/arm32/include/arch/elf.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/elf.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief ARM ELF constants. + */ + +#ifndef KERN_arm32_ELF_H_ +#define KERN_arm32_ELF_H_ + +#define ELF_MACHINE EM_ARM + +#ifdef __BE__ + #define ELF_DATA_ENCODING ELFDATA2MSB +#else + #define ELF_DATA_ENCODING ELFDATA2LSB +#endif + +#define ELF_CLASS ELFCLASS32 + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/exception.h =================================================================== --- kernel/arch/arm32/include/arch/exception.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/exception.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2007 Michal Kebrt, Petr Stepan + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Exception declarations. + */ + +#ifndef KERN_arm32_EXCEPTION_H_ +#define KERN_arm32_EXCEPTION_H_ + +#include +#include + +/** If defined, forces using of high exception vectors. */ +#define HIGH_EXCEPTION_VECTORS + +#ifdef HIGH_EXCEPTION_VECTORS + #define EXC_BASE_ADDRESS 0xffff0000 +#else + #define EXC_BASE_ADDRESS 0x0 +#endif + +/* Exception Vectors */ +#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) +#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) +#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) +#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) +#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) +#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) +#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) + +/* Exception numbers */ +#define EXC_RESET 0 +#define EXC_UNDEF_INSTR 1 +#define EXC_SWI 2 +#define EXC_PREFETCH_ABORT 3 +#define EXC_DATA_ABORT 4 +#define EXC_IRQ 5 +#define EXC_FIQ 6 + +/** Kernel stack pointer. + * + * It is set when thread switches to user mode, + * and then used for exception handling. + * + */ +extern uintptr_t supervisor_sp; + +/** Temporary exception stack pointer. + * + * Temporary stack is used in exceptions handling routines + * before switching to thread's kernel stack. + * + */ +extern uintptr_t exc_stack; + +extern void install_exception_handlers(void); +extern void exception_init(void); +extern void reset_exception_entry(void); +extern void irq_exception_entry(void); +extern void fiq_exception_entry(void); +extern void undef_instr_exception_entry(void); +extern void prefetch_abort_exception_entry(void); +extern void data_abort_exception_entry(void); +extern void swi_exception_entry(void); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/faddr.h =================================================================== --- kernel/arch/arm32/include/arch/faddr.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/faddr.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Function address conversion. + */ + +#ifndef KERN_arm32_FADDR_H_ +#define KERN_arm32_FADDR_H_ + +#include + +/** Calculate absolute address of function referenced by fptr pointer. + * + * @param fptr Function pointer. + * + */ +#define FADDR(fptr) ((uintptr_t) (fptr)) + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/fpu_context.h =================================================================== --- kernel/arch/arm32/include/arch/fpu_context.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/fpu_context.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief FPU context. + */ + +#ifndef KERN_arm32_FPU_CONTEXT_H_ +#define KERN_arm32_FPU_CONTEXT_H_ + +#include + +#define FPU_CONTEXT_ALIGN 8 + +/* ARM Architecture reference manual, p B-1529. + */ +typedef struct { + uint32_t fpexc; + uint32_t fpscr; + uint32_t s[64]; +} fpu_context_t; + +void fpu_setup(void); + +bool handle_if_fpu_exception(void); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/interrupt.h =================================================================== --- kernel/arch/arm32/include/arch/interrupt.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/interrupt.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32interrupt + * @{ + */ +/** @file + * @brief Declarations of interrupt controlling routines. + */ + +#ifndef KERN_arm32_INTERRUPT_H_ +#define KERN_arm32_INTERRUPT_H_ + +#include +#include + +/** Initial size of exception dispatch table. */ +#define IVT_ITEMS 6 + +/** Index of the first item in exception dispatch table. */ +#define IVT_FIRST 0 + +extern void interrupt_init(void); +extern ipl_t interrupts_disable(void); +extern ipl_t interrupts_enable(void); +extern void interrupts_restore(ipl_t ipl); +extern ipl_t interrupts_read(void); +extern bool interrupts_disabled(void); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/istate.h =================================================================== --- kernel/arch/arm32/include/arch/istate.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/istate.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2007 Michal Kebrt, Petr Stepan + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32interrupt + * @{ + */ + +#ifndef KERN_arm32_ISTATE_H_ +#define KERN_arm32_ISTATE_H_ + +#include + +#ifdef KERNEL + +#include + +#else /* KERNEL */ + +#include + +#endif /* KERNEL */ + +/** Struct representing CPU state saved when an exception occurs. */ +typedef struct istate { + uint32_t dummy; + uint32_t spsr; + uint32_t sp; + uint32_t lr; + + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t fp; + uint32_t r12; + + uint32_t pc; +} istate_t; + +/** Set Program Counter member of given istate structure. + * + * @param istate istate structure + * @param retaddr new value of istate's PC member + * + */ +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) +{ + istate->pc = retaddr; +} + +/** Return true if exception happened while in userspace. */ +NO_TRACE static inline int istate_from_uspace(istate_t *istate) +{ + return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; +} + +/** Return Program Counter member of given istate structure. */ +NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate) +{ + return istate->pc; +} + +NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate) +{ + return istate->fp; +} + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mach/beagleboardxm/beagleboardxm.h =================================================================== --- kernel/arch/arm32/include/arch/mach/beagleboardxm/beagleboardxm.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mach/beagleboardxm/beagleboardxm.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm beagleboardxm + * @brief BeagleBoard-xM platform. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief BeagleBoard platform driver. + */ + +#ifndef KERN_arm32_beagleboardxm_H_ +#define KERN_arm32_beagleboardxm_H_ + +#include + +extern struct arm_machine_ops bbxm_machine_ops; + +#endif + +/** @} + */ + Index: kernel/arch/arm32/include/arch/mach/beaglebone/beaglebone.h =================================================================== --- kernel/arch/arm32/include/arch/mach/beaglebone/beaglebone.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mach/beaglebone/beaglebone.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2012 Matteo Facchinetti + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beaglebone beaglebone + * @brief BeagleBone platform. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief BeagleBone platform driver. + */ + +#ifndef KERN_arm32_beaglebone_H_ +#define KERN_arm32_beaglebone_H_ + +#include + +extern struct arm_machine_ops bbone_machine_ops; + +#endif + +/** @} + */ + Index: kernel/arch/arm32/include/arch/mach/gta02/gta02.h =================================================================== --- kernel/arch/arm32/include/arch/mach/gta02/gta02.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mach/gta02/gta02.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2010 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32gta02 GTA02 + * @brief Openmoko GTA02 platform. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief Openmoko GTA02 platform driver. + */ + +#ifndef KERN_arm32_gta02_H_ +#define KERN_arm32_gta02_H_ + +#include + +extern struct arm_machine_ops gta02_machine_ops; + +/** Size of GTA02 IRQ number range (starting from 0) */ +#define GTA02_IRQ_COUNT 32 + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mach/integratorcp/integratorcp.h =================================================================== --- kernel/arch/arm32/include/arch/mach/integratorcp/integratorcp.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mach/integratorcp/integratorcp.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2009 Vineeth Pillai + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32integratorcp + * @brief Integratorcp machine specific parts. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief Integratorcp peripheries drivers declarations. + */ + +#ifndef KERN_arm32_icp_H_ +#define KERN_arm32_icp_H_ + +#include + +/** Last interrupt number (beginning from 0) whose status is probed + * from interrupt controller + */ +#define ICP_IRQC_MAX_IRQ 8 +#define ICP_KBD_IRQ 3 +#define ICP_TIMER_IRQ 6 + +/** Timer frequency */ +#define ICP_TIMER_FREQ 10000 + +#define ICP_UART 0x16000000 +#define ICP_KBD 0x18000000 +#define ICP_KBD_STAT 0x04 +#define ICP_KBD_DATA 0x08 +#define ICP_KBD_INTR_STAT 0x10 +#define ICP_RTC 0x13000000 +#define ICP_RTC1_LOAD_OFFSET 0x100 +#define ICP_RTC1_READ_OFFSET 0x104 +#define ICP_RTC1_CTL_OFFSET 0x108 +#define ICP_RTC1_INTRCLR_OFFSET 0x10C +#define ICP_RTC1_INTRSTAT_OFFSET 0x114 +#define ICP_RTC1_BGLOAD_OFFSET 0x118 +#define ICP_RTC_CTL_VALUE 0x00E2 +#define ICP_IRQC 0x14000000 +#define ICP_IRQC_MASK_OFFSET 0xC +#define ICP_IRQC_UNMASK_OFFSET 0x8 +#define ICP_FB 0x00800000 +#define ICP_FB_FRAME (ICP_FB >> 12) +#define ICP_FB_NUM_FRAME 512 +#define ICP_VGA 0xC0000000 +#define ICP_CMCR 0x10000000 +#define ICP_SDRAM_MASK 0x1C +#define ICP_SDRAMCR_OFFSET 0x20 + +typedef struct { + uintptr_t uart; + uintptr_t kbd_ctrl; + uintptr_t kbd_stat; + uintptr_t kbd_data; + uintptr_t kbd_intstat; + uintptr_t rtc; + uintptr_t rtc1_load; + uintptr_t rtc1_read; + uintptr_t rtc1_ctl; + uintptr_t rtc1_intrclr; + uintptr_t rtc1_intrstat; + uintptr_t rtc1_bgload; + uintptr_t irqc; + uintptr_t irqc_mask; + uintptr_t irqc_unmask; + uintptr_t vga; + uintptr_t cmcr; + uintptr_t sdramcr; +} icp_hw_map_t; + + +extern void icp_init(void); +extern void icp_output_init(void); +extern void icp_input_init(void); +extern void icp_timer_irq_start(void); +extern void icp_cpu_halt(void); +extern void icp_irq_exception(unsigned int, istate_t *); +extern void icp_get_memory_extents(uintptr_t *, size_t *); +extern void icp_frame_init(void); +extern size_t icp_get_irq_count(void); +extern const char *icp_get_platform_name(void); + +extern struct arm_machine_ops icp_machine_ops; + +/** Size of IntegratorCP IRQ number range (starting from 0) */ +#define ICP_IRQ_COUNT 8 + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/machine_func.h =================================================================== --- kernel/arch/arm32/include/arch/machine_func.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/machine_func.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * Copyright (c) 2009 Vineeth Pillai + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Declarations of machine specific functions. + * + * These functions enable to differentiate more kinds of ARM emulators + * or CPUs. It's the same concept as "arch" functions on the architecture + * level. + */ + +#ifndef KERN_arm32_MACHINE_FUNC_H_ +#define KERN_arm32_MACHINE_FUNC_H_ + +#include +#include +#include + +struct arm_machine_ops { + void (*machine_init)(void); + void (*machine_timer_irq_start)(void); + void (*machine_cpu_halt)(void); + void (*machine_get_memory_extents)(uintptr_t *, size_t *); + void (*machine_irq_exception)(unsigned int, istate_t *); + void (*machine_frame_init)(void); + void (*machine_output_init)(void); + void (*machine_input_init)(void); + size_t (*machine_get_irq_count)(void); + const char *(*machine_get_platform_name)(void); +}; + +/** Pointer to arm_machine_ops structure being used. */ +extern struct arm_machine_ops *machine_ops; + +/** Initialize machine_ops pointer. */ +extern void machine_ops_init(void); + +/** Maps HW devices to the kernel address space using #hw_map. */ +extern void machine_init(void); + + +/** Starts timer. */ +extern void machine_timer_irq_start(void); + + +/** Halts CPU. */ +extern void machine_cpu_halt(void); + +/** Get extents of available memory. + * + * @param start Place to store memory start address. + * @param size Place to store memory size. + */ +extern void machine_get_memory_extents(uintptr_t *start, size_t *size); + +/** Interrupt exception handler. + * + * @param exc_no Interrupt exception number. + * @param istate Saved processor state. + */ +extern void machine_irq_exception(unsigned int exc_no, istate_t *istate); + + +/* + * Machine specific frame initialization + */ +extern void machine_frame_init(void); + +/* + * configure the serial line output device. + */ +extern void machine_output_init(void); + +/* + * configure the serial line input device. + */ +extern void machine_input_init(void); + +extern size_t machine_get_irq_count(void); + +extern const char * machine_get_platform_name(void); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/as.h =================================================================== --- kernel/arch/arm32/include/arch/mm/as.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/as.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Address space manipulating functions declarations. + */ + +#ifndef KERN_arm32_AS_H_ +#define KERN_arm32_AS_H_ + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 + +#define KERNEL_ADDRESS_SPACE_START_ARCH UINT32_C(0x80000000) +#define KERNEL_ADDRESS_SPACE_END_ARCH UINT32_C(0xffffffff) +#define USER_ADDRESS_SPACE_START_ARCH UINT32_C(0x00000000) +#define USER_ADDRESS_SPACE_END_ARCH UINT32_C(0x7fffffff) + +typedef struct { +} as_arch_t; + +#include + +#define as_constructor_arch(as, flags) (as != as) +#define as_destructor_arch(as) (as != as) +#define as_create_arch(as, flags) (as != as) +#define as_deinstall_arch(as) +#define as_invalidate_translation_cache(as, page, cnt) + +extern void as_arch_init(void); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/asid.h =================================================================== --- kernel/arch/arm32/include/arch/mm/asid.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/asid.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief ASIDs related declarations. + * + * ARM CPUs doesn't support ASIDs. + */ + +#ifndef KERN_arm32_ASID_H_ +#define KERN_arm32_ASID_H_ + +#include + +#define ASID_MAX_ARCH 3 /* minimal required number */ + +typedef uint8_t asid_t; + +/* + * This works due to fact that this file is never included alone but only + * through "generic/include/mm/asid.h" where ASID_START is defined. + */ +#define asid_get() (ASID_START + 1) + +#define asid_put(asid) + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/frame.h =================================================================== --- kernel/arch/arm32/include/arch/mm/frame.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/frame.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Frame related declarations. + */ + +#ifndef KERN_arm32_FRAME_H_ +#define KERN_arm32_FRAME_H_ + +#define FRAME_WIDTH 12 /* 4KB frames */ +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#ifndef __ASM__ + +#include + +#define BOOT_PAGE_TABLE_SIZE 0x4000 + +#ifdef MACHINE_gta02 + +#define PHYSMEM_START_ADDR 0x30008000 +#define BOOT_PAGE_TABLE_ADDRESS 0x30010000 + +#elif defined MACHINE_beagleboardxm + +#define PHYSMEM_START_ADDR 0x80000000 +#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 + +#elif defined MACHINE_beaglebone + +#define PHYSMEM_START_ADDR 0x80000000 +#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 + +#else + +#define PHYSMEM_START_ADDR 0x00000000 +#define BOOT_PAGE_TABLE_ADDRESS 0x00008000 + +#endif + +#define BOOT_PAGE_TABLE_START_FRAME (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH) +#define BOOT_PAGE_TABLE_SIZE_IN_FRAMES (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH) + +extern void frame_low_arch_init(void); +extern void frame_high_arch_init(void); +extern void boot_page_table_free(void); +#define physmem_print() + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/km.h =================================================================== --- kernel/arch/arm32/include/arch/mm/km.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/km.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2011 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + */ + +#ifndef KERN_arm32_KM_H_ +#define KERN_arm32_KM_H_ + +#include + +#define KM_ARM32_IDENTITY_START UINT32_C(0x80000000) +#define KM_ARM32_IDENTITY_SIZE UINT32_C(0x70000000) + +#define KM_ARM32_NON_IDENTITY_START UINT32_C(0xf0000000) +/* + * The last virtual megabyte contains the high exception vectors (0xFFFF0000). + * Do not include this range into kernel non-identity. + */ +#define KM_ARM32_NON_IDENTITY_SIZE UINT32_C(0x0ff00000) + +extern void km_identity_arch_init(void); +extern void km_non_identity_arch_init(void); +extern bool km_is_non_identity_arch(uintptr_t); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/page.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/page.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_H_ +#define KERN_arm32_PAGE_H_ + +#include +#include +#include +#include +#include + +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#if (defined MACHINE_beagleboardxm) || (defined MACHINE_beaglebone) +#ifndef __ASM__ +# define KA2PA(x) ((uintptr_t) (x)) +# define PA2KA(x) ((uintptr_t) (x)) +#else +# define KA2PA(x) (x) +# define PA2KA(x) (x) +#endif +#else +#ifndef __ASM__ +# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) +# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) +#else +# define KA2PA(x) ((x) - 0x80000000) +# define PA2KA(x) ((x) + 0x80000000) +#endif +#endif + +/* Number of entries in each level. */ +#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 +/* coarse page tables used (256 * 4 = 1KB per page) */ +#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ + +/* Page table sizes for each level. */ +#define PTL0_SIZE_ARCH FOUR_FRAMES +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME + +/* Macros calculating indices into page tables for each level. */ +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) + +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) + +/* Set PTE address accessors for each level. */ +#define SET_PTL0_ADDRESS_ARCH(ptl0) \ + (set_ptl0_addr((pte_t *) (ptl0))) +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ + (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) +#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) +#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ + (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) + +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) + +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) +#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) +#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x)) + +/* Set PTE present bit accessors for each level. */ +#define SET_PTL1_PRESENT_ARCH(ptl0, i) \ + set_pt_level0_present((pte_t *) (ptl0), (size_t) (i)) +#define SET_PTL2_PRESENT_ARCH(ptl1, i) +#define SET_PTL3_PRESENT_ARCH(ptl2, i) +#define SET_FRAME_PRESENT_ARCH(ptl3, i) \ + set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) + +#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a) +#include "page_armv6.h" +#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5) +#include "page_armv4.h" +#else +#error "Unsupported architecture" +#endif + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv4_H_ +#define KERN_arm32_PAGE_armv4_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) +#define PTE_EXECUTABLE_ARCH(pte) \ + 1 + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned impl_specific : 3; + unsigned domain : 4; + unsigned should_be_zero : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + + /* access permissions for each of 4 subparts of a page + * (for each 1KB when small pages used */ + unsigned access_permission_0 : 2; + unsigned access_permission_1 : 2; + unsigned access_permission_2 : 2; + unsigned access_permission_3 : 2; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP_USER_NO_KERNEL_RW 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP_USER_RO_KERNEL_RW 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP_USER_RW_KERNEL_RW 3 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + int dt = p->descriptor_type; + int ap = p->access_permission_0; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | + ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; + + /* default access permission */ + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_NO_KERNEL_RW; + + if (flags & PAGE_USER) { + if (flags & PAGE_READ) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RO_KERNEL_RW; + } + if (flags & PAGE_WRITE) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RW_KERNEL_RW; + } + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv6.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/page_armv6.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv7_H_ +#define KERN_arm32_PAGE_armv7_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO) +#define PTE_EXECUTABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.descriptor_type != PTE_DESCRIPTOR_SMALL_PAGE_NX) + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned pxn : 1; + unsigned ns : 1; + unsigned should_be_zero_0 : 1; + unsigned domain : 4; + unsigned should_be_zero_1 : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages, 0b11 for NX small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + unsigned access_permission_0 : 2; + unsigned tex : 3; + unsigned access_permission_1 : 1; + unsigned shareable : 1; + unsigned non_global : 1; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP0_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP0_USER_NO_KERNEL_FULL 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP0_USER_LIMITED_KERNEL_FULL 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP0_USER_FULL_KERNEL_FULL 3 + +/** Allow writes */ +#define PTE_AP1_RO 1 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + +/** pte_level1_t small page table flag with NX (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + const pte_level0_t *p = &pt[i].l0; + const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + const pte_level1_t *p = &pt[i].l1; + + const unsigned dt = p->descriptor_type; + const unsigned ap0 = p->access_permission_0; + const unsigned ap1 = p->access_permission_1; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) | + ((ap0 == PTE_AP0_USER_LIMITED_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_FULL_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 != PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_USER_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_FULL_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_NO_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero_0 = 1; + p->should_be_zero_1 = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + p->domain = 0; + p->ns = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + } else { + if (flags & PAGE_EXEC) + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; + } + + /* tex=0 buf=1 and cache=1 => normal memory + * tex=0 buf=1 and cache=0 => shareable device mmio + */ + p->cacheable = (flags & PAGE_CACHEABLE); + p->bufferable = 1; + p->tex = 0; + + /* Shareable is ignored for devices (non-cacheable), + * turn it on for normal memory. */ + p->shareable = 1; + + p->non_global = !(flags & PAGE_GLOBAL); + + /* default access permission: kernel only*/ + p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL; + + if (flags & PAGE_USER) { + p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL; + // TODO Fix kernel to use PAGE_WRITE flag properly and + // apply this for kernel pages as well. + if (!(flags & PAGE_WRITE)) + p->access_permission_1 = PTE_AP1_RO; + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/page_fault.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_fault.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/page_fault.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Page fault related declarations. + */ + +#ifndef KERN_arm32_PAGE_FAULT_H_ +#define KERN_arm32_PAGE_FAULT_H_ + +#include + + +/** Decribes CP15 "fault status register" (FSR). + * + * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR. + * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of + * the architecture. A write flag (bit[11] of the DFSR) has also been + * introduced." + * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719) + * + * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). for FSR info + */ +typedef union { + struct { + unsigned status : 4; + unsigned domain : 4; + unsigned zero : 1; + unsigned lpae : 1; /**< Needs LPAE support implemented */ + unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */ + unsigned wr : 1; /**< armv6+ only */ + unsigned ext : 1 ; /**< external abort */ + unsigned cm : 1; /**< Cache maintenance, needs LPAE support */ + unsigned should_be_zero : 18; + } data; + struct { + unsigned status : 4; + unsigned sbz0 : 6; + unsigned fs : 1; + unsigned should_be_zero : 21; + } inst; + uint32_t raw; +} fault_status_t; + + +/** Simplified description of instruction code. + * + * @note Used for recognizing memory access instructions. + * @see ARM architecture reference (chapter 3.1) + */ +typedef struct { + unsigned dummy1 : 4; + unsigned bit4 : 1; + unsigned bits567 : 3; + unsigned dummy : 12; + unsigned access : 1; + unsigned opcode : 4; + unsigned type : 3; + unsigned condition : 4; +} ATTRIBUTE_PACKED instruction_t; + + +/** Help union used for casting pc register (uint_32_t) value into + * #instruction_t pointer. + */ +typedef union { + instruction_t *instr; + uint32_t pc; +} instruction_union_t; + +extern void prefetch_abort(unsigned int, istate_t *); +extern void data_abort(unsigned int, istate_t *); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/mm/tlb.h =================================================================== --- kernel/arch/arm32/include/arch/mm/tlb.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/mm/tlb.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2007 Pavel Jancik + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief TLB related declarations. + */ + +#ifndef KERN_arm32_TLB_H_ +#define KERN_arm32_TLB_H_ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/proc/task.h =================================================================== --- kernel/arch/arm32/include/arch/proc/task.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/proc/task.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32proc + * @{ + */ +/** @file + * @brief Task related declarations. + */ + +#ifndef KERN_arm32_TASK_H_ +#define KERN_arm32_TASK_H_ + +typedef struct { +} task_arch_t; + +#define task_create_arch(t) +#define task_destroy_arch(t) + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/proc/thread.h =================================================================== --- kernel/arch/arm32/include/arch/proc/thread.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/proc/thread.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32proc + * @{ + */ +/** @file + * @brief Thread related declarations. + */ + +#ifndef KERN_arm32_THREAD_H_ +#define KERN_arm32_THREAD_H_ + +typedef struct { +} thread_arch_t; + +#define thr_constructor_arch(t) +#define thr_destructor_arch(t) +#define thread_create_arch(t) + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/ras.h =================================================================== --- kernel/arch/arm32/include/arch/ras.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/ras.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2009 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Declarations related to Restartable Atomic Sequences. + */ + +#ifndef KERN_arm32_RAS_H_ +#define KERN_arm32_RAS_H_ + +#include +#include + +#define RAS_START 0 +#define RAS_END 1 + +extern uintptr_t *ras_page; + +extern void ras_init(void); +extern void ras_check(unsigned int, istate_t *); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/regutils.h =================================================================== --- kernel/arch/arm32/include/arch/regutils.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/regutils.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2007 Petr Stepan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** + * @file + * @brief Utilities for convenient manipulation with ARM registers. + */ + +#ifndef KERN_arm32_REGUTILS_H_ +#define KERN_arm32_REGUTILS_H_ + +#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) +#define STATUS_REG_MODE_MASK 0x1f + +/* ARM Processor Operation Modes */ +enum { + USER_MODE = 0x10, + FIQ_MODE = 0x11, + IRQ_MODE = 0x12, + SUPERVISOR_MODE = 0x13, + MONITOR_MODE = 0x16, + ABORT_MODE = 0x17, + HYPERVISOR_MODE = 0x1a, + UNDEFINED_MODE = 0x1b, + SYSTEM_MODE = 0x1f, + MODE_MASK = 0x1f, +}; +/* [CS]PRS manipulation macros */ +#define GEN_STATUS_READ(nm, reg) \ + static inline uint32_t nm## _status_reg_read(void) \ + { \ + uint32_t retval; \ + \ + asm volatile ( \ + "mrs %[retval], " #reg \ + : [retval] "=r" (retval) \ + ); \ + \ + return retval; \ + } + +#define GEN_STATUS_WRITE(nm, reg, fieldname, field) \ + static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ + { \ + asm volatile ( \ + "msr " #reg "_" #field ", %[value]" \ + :: [value] "r" (value) \ + ); \ + } + +/** Return the value of CPSR (Current Program Status Register). */ +GEN_STATUS_READ(current, cpsr); + +/** Set control bits of CPSR. */ +GEN_STATUS_WRITE(current, cpsr, control, c); + +/** Return the value of SPSR (Saved Program Status Register). */ +GEN_STATUS_READ(saved, spsr); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/security_ext.h =================================================================== --- kernel/arch/arm32/include/arch/security_ext.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/security_ext.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Security Extensions Routines + */ + +#ifndef KERN_arm32_SECURITY_EXT_H_ +#define KERN_arm32_SECURITY_EXT_H_ + +#include +#include + +/** Test whether the current cpu supports security extensions. + * return true if security extensions are supported, false otherwise. + * @note The Processor Feature Register 1 that provides this information + * is available only on armv7+. This function returns false on all\ + * older archs. + */ +static inline bool sec_ext_is_implemented() +{ +#ifdef PROCESSOR_ARCH_armv7_a + const uint32_t idpfr = ID_PFR1_read() & ID_PFR1_SEC_EXT_MASK; + return idpfr == ID_PFR1_SEC_EXT || idpfr == ID_PFR1_SEC_EXT_RFR; +#endif + return false; +} + +/** Test whether we are running in monitor mode. + * return true, if the current mode is Monitor mode, false otherwise. + * @note this is safe to call even on machines that do not implement monitor + * mode. + */ +static inline bool sec_ext_is_monitor_mode() +{ + return (current_status_reg_read() & MODE_MASK) == MONITOR_MODE; +} + +/** Test whether we are running in a secure state. + * return true if the current state is secure, false otherwise. + * + * @note: This functions will cause undef isntruction trap if we + * are not running in the secure state. + * + * @note: u-boot enables non-secure access to cp 10/11, as well as some other + * features and switches to non-secure state during boot. + * Look for 'secureworld_exit' in arch/arm/cpu/armv7/omap3/board.c. + */ +static inline bool sec_ext_is_secure() +{ + return sec_ext_is_implemented() + && (sec_ext_is_monitor_mode() || !(SCR_read() & SCR_NS_FLAG)); +} + +#endif +/** @} + */ Index: kernel/arch/arm32/include/arch/stack.h =================================================================== --- kernel/arch/arm32/include/arch/stack.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/stack.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Stack constants. + */ + +#ifndef KERN_arm32_STACK_H_ +#define KERN_arm32_STACK_H_ + +#define STACK_ITEM_SIZE 4 + +/** See ABI for + * details + */ +#define STACK_ALIGNMENT 8 + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/arch/types.h =================================================================== --- kernel/arch/arm32/include/arch/types.h (revision 850235d404a93a3e011befe27ef139ef8e288759) +++ kernel/arch/arm32/include/arch/types.h (revision 850235d404a93a3e011befe27ef139ef8e288759) @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Type definitions. + */ + +#ifndef KERN_arm32_TYPES_H_ +#define KERN_arm32_TYPES_H_ + +#ifndef DOXYGEN + #define ATTRIBUTE_PACKED __attribute__((packed)) +#else + #define ATTRIBUTE_PACKED +#endif + +typedef uint32_t size_t; +typedef int32_t ssize_t; + +typedef uint32_t uintptr_t; +typedef uint32_t pfn_t; + +typedef uint32_t ipl_t; + +typedef uint32_t sysarg_t; +typedef int32_t native_t; +typedef uint32_t atomic_count_t; + +typedef struct { +} fncptr_t; + +#define INTN_C(c) INT32_C(c) +#define UINTN_C(c) UINT32_C(c) + +#define PRIdn PRId32 /**< Format for native_t. */ +#define PRIun PRIu32 /**< Format for sysarg_t. */ +#define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ +#define PRIua PRIu32 /**< Format for atomic_count_t. */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/asm.h =================================================================== --- kernel/arch/arm32/include/asm.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,124 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Declarations of functions implemented in assembly. - */ - -#ifndef KERN_arm32_ASM_H_ -#define KERN_arm32_ASM_H_ - -#include -#include -#include -#include -#include - -/** CPU specific way to sleep cpu. - * - * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi). - * ARM920T has custom coprocessor action to do the same. See ARM920T Technical - * Reference Manual ch 4.9 p. 4-23 (103 in the PDF) - * ARM926EJ-S uses the same coprocessor instruction as ARM920T. See ARM926EJ-S - * chapter 2.3.8 p.2-22 (52 in the PDF) - * - * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture - * reference manual for armv4/5 CP15 implementation is mandatory only for - * armv6+. - */ -NO_TRACE static inline void cpu_sleep(void) -{ -#ifdef PROCESSOR_ARCH_armv7_a - asm volatile ( "wfe" ); -#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t) - asm volatile ( "mcr p15, 0, R0, c7, c0, 4" ); -#endif -} - -NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) -{ - *port = v; -} - -NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) -{ - *port = v; -} - -NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) -{ - *port = v; -} - -NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) -{ - return *port; -} - -NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) -{ - return *port; -} - -NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) -{ - return *port; -} - -/** Return base address of current stack. - * - * Return the base address of the current stack. - * The stack is assumed to be STACK_SIZE bytes long. - * The stack must start on page boundary. - * - */ -NO_TRACE static inline uintptr_t get_stack_base(void) -{ - uintptr_t v; - - asm volatile ( - "and %[v], sp, %[size]\n" - : [v] "=r" (v) - : [size] "r" (~(STACK_SIZE - 1)) - ); - - return v; -} - -extern void cpu_halt(void) __attribute__((noreturn)); -extern void asm_delay_loop(uint32_t t); -extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, - uintptr_t entry); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/asm/boot.h =================================================================== --- kernel/arch/arm32/include/asm/boot.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,45 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Initial kernel start. - */ - -#ifndef KERN_arm32_ASM_BOOT_H_ -#define KERN_arm32_ASM_BOOT_H_ - -/** Size of a temporary stack used for initial kernel start. */ -#define TEMP_STACK_SIZE 0x100 - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/atomic.h =================================================================== --- kernel/arch/arm32/include/atomic.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,131 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Atomic operations. - */ - -#ifndef KERN_arm32_ATOMIC_H_ -#define KERN_arm32_ATOMIC_H_ - -#include -#include - -/** Atomic addition. - * - * @param val Where to add. - * @param i Value to be added. - * - * @return Value after addition. - * - */ -NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, - atomic_count_t i) -{ - /* - * This implementation is for UP pre-ARMv6 systems where we do not have - * the LDREX and STREX instructions. - */ - ipl_t ipl = interrupts_disable(); - val->count += i; - atomic_count_t ret = val->count; - interrupts_restore(ipl); - - return ret; -} - -/** Atomic increment. - * - * @param val Variable to be incremented. - * - */ -NO_TRACE static inline void atomic_inc(atomic_t *val) -{ - atomic_add(val, 1); -} - -/** Atomic decrement. - * - * @param val Variable to be decremented. - * - */ -NO_TRACE static inline void atomic_dec(atomic_t *val) { - atomic_add(val, -1); -} - -/** Atomic pre-increment. - * - * @param val Variable to be incremented. - * @return Value after incrementation. - * - */ -NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) -{ - return atomic_add(val, 1); -} - -/** Atomic pre-decrement. - * - * @param val Variable to be decremented. - * @return Value after decrementation. - * - */ -NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) -{ - return atomic_add(val, -1); -} - -/** Atomic post-increment. - * - * @param val Variable to be incremented. - * @return Value before incrementation. - * - */ -NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) -{ - return atomic_add(val, 1) - 1; -} - -/** Atomic post-decrement. - * - * @param val Variable to be decremented. - * @return Value before decrementation. - * - */ -NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) -{ - return atomic_add(val, -1) + 1; -} - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/barrier.h =================================================================== --- kernel/arch/arm32/include/barrier.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,131 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Memory barriers. - */ - -#ifndef KERN_arm32_BARRIER_H_ -#define KERN_arm32_BARRIER_H_ - -#ifdef KERNEL -#include -#else -#include -#endif - -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") - -#if defined PROCESSOR_ARCH_armv7_a -/* ARMv7 uses instructions for memory barriers see ARM Architecture reference - * manual for details: - * DMB: ch. A8.8.43 page A8-376 - * DSB: ch. A8.8.44 page A8-378 - * See ch. A3.8.3 page A3-148 for details about memory barrier implementation - * and functionality on armv7 architecture. - */ -#define memory_barrier() asm volatile ("dmb" ::: "memory") -#define read_barrier() asm volatile ("dsb" ::: "memory") -#define write_barrier() asm volatile ("dsb st" ::: "memory") -#define inst_barrier() asm volatile ("isb" ::: "memory") -#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL -/* - * ARMv6 introduced user access of the following commands: - * - Prefetch flush - * - Data synchronization barrier - * - Data memory barrier - * - Clean and prefetch range operations. - * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4 - */ -/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions. - * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs, - * CP15 implementation is mandatory only for armv6+. - */ -#define memory_barrier() CP15DMB_write(0) -#define read_barrier() CP15DSB_write(0) -#define write_barrier() read_barrier() -#define inst_barrier() CP15ISB_write(0) -#else -/* Older manuals mention syscalls as a way to implement cache coherency and - * barriers. See for example ARM Architecture Reference Manual Version D - * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28) - */ -// TODO implement on per PROCESSOR basis or via syscalls -#define memory_barrier() asm volatile ("" ::: "memory") -#define read_barrier() asm volatile ("" ::: "memory") -#define write_barrier() asm volatile ("" ::: "memory") -#define inst_barrier() asm volatile ("" ::: "memory") -#endif - -/* - * There are multiple ways ICache can be implemented on ARM machines. Namely - * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference - * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum - * compatibility across processors, ARM recommends that operating systems target - * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, - * and do not assume the presence of the IVIPT extension. Software that relies - * on the IVIPT extension might fail in an unpredictable way on an ARMv7 - * implementation that does not include the IVIPT extension." (7.2.6 p. 245). - * Only PIPT invalidates cache for all VA aliases if one block is invalidated. - * - * @note: Supporting ASID and VMID tagged VIVT may need to add ICache - * maintenance to other places than just smc. - */ - -#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL -/* Available on all supported arms, - * invalidates entire ICache so the written value does not matter. */ -//TODO might be PL1 only on armv5- -#define smc_coherence(a) \ -do { \ - DCCMVAU_write((uint32_t)(a)); /* Flush changed memory */\ - write_barrier(); /* Wait for completion */\ - ICIALLU_write(0); /* Flush ICache */\ - inst_barrier(); /* Wait for Inst refetch */\ -} while (0) -/* @note: Cache type register is not available in uspace. We would need - * to export the cache line value, or use syscall for uspace smc_coherence */ -#define smc_coherence_block(a, l) \ -do { \ - for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\ - smc_coherence(addr); \ -} while (0) -#else -#define smc_coherence(a) -#define smc_coherence_block(a, l) -#endif - - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/cache.h =================================================================== --- kernel/arch/arm32/include/cache.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,50 +1,0 @@ -/* - * Copyright (c) 2013 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Security Extensions Routines - */ - -#ifndef KERN_arm32_CACHE_H_ -#define KERN_arm32_CACHE_H_ - -unsigned dcache_levels(void); - -void dcache_flush(void); -void dcache_flush_invalidate(void); -void cpu_dcache_flush(void); -void cpu_dcache_flush_invalidate(void); -void icache_invalidate(void); - -#endif -/** @} - */ - Index: kernel/arch/arm32/include/context.h =================================================================== --- kernel/arch/arm32/include/context.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,82 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Thread context. - */ - -#ifndef KERN_arm32_CONTEXT_H_ -#define KERN_arm32_CONTEXT_H_ - -#include -#include - -/* Put one item onto the stack to support get_stack_base() and align it up. */ -#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) - -#define context_set(c, _pc, stack, size) \ - do { \ - (c)->pc = (uintptr_t) (_pc); \ - (c)->sp = ((uintptr_t) (stack)) + (size) - SP_DELTA; \ - (c)->fp = 0; \ - } while (0) - -#ifndef __ASM__ - -#include - -/** Thread context containing registers that must be preserved across function - * calls. - */ -typedef struct { - uint32_t cpu_mode; - uintptr_t sp; - uintptr_t pc; - - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t fp; /* r11 */ - - ipl_t ipl; -} context_t; - - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/cp15.h =================================================================== --- kernel/arch/arm32/include/cp15.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,525 +1,0 @@ -/* - * Copyright (c) 2013 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief System Control Coprocessor (CP15) - */ - -#ifndef KERN_arm32_CP15_H_ -#define KERN_arm32_CP15_H_ - - -/** See ARM Architecture reference manual ch. B3.17.1 page B3-1456 - * for the list */ - -#define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \ -static inline uint32_t name##_read() \ -{ \ - uint32_t val; \ - asm volatile ( "mrc p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" : "=r" (val) ); \ - return val; \ -} -#define CONTROL_REG_GEN_WRITE(name, crn, opc1, crm, opc2) \ -static inline void name##_write(uint32_t val) \ -{ \ - asm volatile ( "mcr p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" :: "r" (val) ); \ -} - -/* Identification registers */ -enum { - MIDR_IMPLEMENTER_MASK = 0xff, - MIDR_IMPLEMENTER_SHIFT = 24, - MIDR_VARIANT_MASK = 0xf, - MIDR_VARIANT_SHIFT = 20, - MIDR_ARCHITECTURE_MASK = 0xf, - MIDR_ARCHITECTURE_SHIFT = 16, - MIDR_PART_NUMBER_MASK = 0xfff, - MIDR_PART_NUMBER_SHIFT = 4, - MIDR_REVISION_MASK = 0xf, - MIDR_REVISION_SHIFT = 0, -}; -CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0); - -enum { - CTR_FORMAT_MASK = 0xe0000000, - CTR_FORMAT_ARMv7 = 0x80000000, - CTR_FORMAT_ARMv6 = 0x00000000, - /* ARMv7 format */ - CTR_CWG_MASK = 0xf, - CTR_CWG_SHIFT = 24, - CTR_ERG_MASK = 0xf, - CTR_ERG_SHIFT = 20, - CTR_D_MIN_LINE_MASK = 0xf, - CTR_D_MIN_LINE_SHIFT = 16, - CTR_I_MIN_LINE_MASK = 0xf, - CTR_I_MIN_LINE_SHIFT = 0, - CTR_L1I_POLICY_MASK = 0x0000c000, - CTR_L1I_POLICY_AIVIVT = 0x00004000, - CTR_L1I_POLICY_VIPT = 0x00008000, - CTR_L1I_POLICY_PIPT = 0x0000c000, - /* ARMv6 format */ - CTR_CTYPE_MASK = 0x1e000000, - CTR_CTYPE_WT = 0x00000000, - CTR_CTYPE_WB_NL = 0x04000000, - CTR_CTYPE_WB_D = 0x0a000000, - CTR_CTYPE_WB_A = 0x0c000000, /**< ARMv5- only */ - CTR_CTYPE_WB_B = 0x0e000000, /**< ARMv5- only */ - CTR_CTYPE_WB_C = 0x1c000000, - CTR_SEP_FLAG = 1 << 24, - CTR_DCACHE_P_FLAG = 1 << 23, - CTR_DCACHE_SIZE_MASK = 0xf, - CTR_DCACHE_SIZE_SHIFT = 18, - CTR_DCACHE_ASSOC_MASK = 0x7, - CTR_DCACHE_ASSOC_SHIFT = 15, - CTR_DCACHE_M_FLAG = 1 << 14, - CTR_DCACHE_LEN_MASK = 0x3, - CTR_DCACHE_LEN_SHIFT = 0, - CTR_ICACHE_P_FLAG = 1 << 11, - CTR_ICACHE_SIZE_MASK = 0xf, - CTR_ICACHE_SIZE_SHIFT = 6, - CTR_ICACHE_ASSOC_MASK = 0x7, - CTR_ICACHE_ASSOC_SHIFT = 3, - CTR_ICACHE_M_FLAG = 1 << 2, - CTR_ICACHE_LEN_MASK = 0x3, - CTR_ICACHE_LEN_SHIFT = 0, -}; -CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1); -CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2); -CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3); -CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5); -CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6); - -enum { - ID_PFR0_THUMBEE_MASK = 0xf << 12, - ID_PFR0_THUMBEE = 0x1 << 12, - ID_PFR0_JAZELLE_MASK = 0xf << 8, - ID_PFR0_JAZELLE = 0x1 << 8, - ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8, - ID_PFR0_THUMB_MASK = 0xf << 4, - ID_PFR0_THUMB = 0x1 << 4, - ID_PFR0_THUMB2 = 0x3 << 4, - ID_PFR0_ARM_MASK = 0xf << 0, - ID_PFR0_ARM = 0x1 << 0, -}; -CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0); - -enum { - ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16, - ID_PFR1_GEN_TIMER_EXT = 0x1 << 16, - ID_PFR1_VIRT_EXT_MASK = 0xf << 12, - ID_PFR1_VIRT_EXT = 0x1 << 12, - ID_PFR1_M_PROF_MASK = 0xf << 8, - ID_PFR1_M_PROF_MODEL = 0x2 << 8, - ID_PFR1_SEC_EXT_MASK = 0xf << 4, - ID_PFR1_SEC_EXT = 0x1 << 4, - ID_PFR1_SEC_EXT_RFR = 0x2 << 4, - ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0, - ID_PFR1_ARMV4_MODEL = 0x1 << 0, -}; -CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1); -CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2); -CONTROL_REG_GEN_READ(ID_AFR0, c0, 0, c1, 3); -CONTROL_REG_GEN_READ(ID_MMFR0, c0, 0, c1, 4); -CONTROL_REG_GEN_READ(ID_MMFR1, c0, 0, c1, 5); -CONTROL_REG_GEN_READ(ID_MMFR2, c0, 0, c1, 6); -CONTROL_REG_GEN_READ(ID_MMFR3, c0, 0, c1, 7); - -CONTROL_REG_GEN_READ(ID_ISAR0, c0, 0, c2, 0); -CONTROL_REG_GEN_READ(ID_ISAR1, c0, 0, c2, 1); -CONTROL_REG_GEN_READ(ID_ISAR2, c0, 0, c2, 2); -CONTROL_REG_GEN_READ(ID_ISAR3, c0, 0, c2, 3); -CONTROL_REG_GEN_READ(ID_ISAR4, c0, 0, c2, 4); -CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5); - -enum { - CCSIDR_WT_FLAG = 1 << 31, - CCSIDR_WB_FLAG = 1 << 30, - CCSIDR_RA_FLAG = 1 << 29, - CCSIDR_WA_FLAG = 1 << 28, - CCSIDR_NUMSETS_MASK = 0x7fff, - CCSIDR_NUMSETS_SHIFT = 13, - CCSIDR_ASSOC_MASK = 0x3ff, - CCSIDR_ASSOC_SHIFT = 3, - CCSIDR_LINESIZE_MASK = 0x7, - CCSIDR_LINESIZE_SHIFT = 0, -}; -CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0); - -enum { - CLIDR_LOUU_MASK = 0x7, - CLIDR_LOUU_SHIFT = 27, - CLIDR_LOC_MASK = 0x7, - CLIDR_LOC_SHIFT = 24, - CLIDR_LOUIS_MASK = 0x7, - CLIDR_LOUIS_SHIFT = 21, - CLIDR_NOCACHE = 0x0, - CLIDR_ICACHE_ONLY = 0x1, - CLIDR_DCACHE_ONLY = 0x2, - CLIDR_SEP_CACHE = 0x3, - CLIDR_UNI_CACHE = 0x4, - CLIDR_CACHE_MASK = 0x7, -#define CLIDR_CACHE(level, val) ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK) -}; -CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1); -CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */ - -enum { - CCSELR_LEVEL_MASK = 0x7, - CCSELR_LEVEL_SHIFT = 1, - CCSELR_INSTRUCTION_FLAG = 1 << 0, -}; -CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0); -CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0); -CONTROL_REG_GEN_READ(VPIDR, c0, 4, c0, 0); -CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0); -CONTROL_REG_GEN_READ(VMPIDR, c0, 4, c0, 5); -CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5); - -/* System control registers */ -/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference - * Manual ARMv7-A and ARMv7-R edition, page 1687 */ -enum { - SCTLR_MMU_EN_FLAG = 1 << 0, - SCTLR_ALIGN_CHECK_EN_FLAG = 1 << 1, /* Allow alignemnt check */ - SCTLR_CACHE_EN_FLAG = 1 << 2, - SCTLR_CP15_BARRIER_EN_FLAG = 1 << 5, - SCTLR_B_EN_FLAG = 1 << 7, /* ARMv6-, big endian switch */ - SCTLR_SWAP_EN_FLAG = 1 << 10, - SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11, - SCTLR_INST_CACHE_EN_FLAG = 1 << 12, - SCTLR_HIGH_VECTORS_EN_FLAG = 1 << 13, - SCTLR_ROUND_ROBIN_EN_FLAG = 1 << 14, - SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17, - SCTLR_WRITE_XN_EN_FLAG = 1 << 19, /* Only if virt. supported */ - SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */ - SCTLR_FAST_IRQ_EN_FLAG = 1 << 21, /* Disable impl. specific feat*/ - SCTLR_UNALIGNED_EN_FLAG = 1 << 22, /* Must be 1 on armv7 */ - SCTLR_IRQ_VECTORS_EN_FLAG = 1 << 24, - SCTLR_BIG_ENDIAN_EXC_FLAG = 1 << 25, - SCTLR_NMFI_EN_FLAG = 1 << 27, - SCTLR_TEX_REMAP_EN_FLAG = 1 << 28, - SCTLR_ACCESS_FLAG_EN_FLAG = 1 << 29, - SCTLR_THUMB_EXC_EN_FLAG = 1 << 30, -}; -CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0); -CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0); -CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1); -CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1); - -enum { - CPACR_ASEDIS_FLAG = 1 << 31, - CPACR_D32DIS_FLAG = 1 << 30, - CPACR_TRCDIS_FLAG = 1 << 28, -#define CPACR_CP_MASK(cp) (0x3 << (cp * 2)) -#define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2)) -#define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2)) -#define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2)) -}; -CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2); -CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2); - -/* Implemented as part of Security extensions */ -enum { - SCR_SIF_FLAG = 1 << 9, - SCR_HCE_FLAG = 1 << 8, - SCR_SCD_FLAG = 1 << 7, - SCR_nET_FLAG = 1 << 6, - SCR_AW_FLAG = 1 << 5, - SCR_FW_FLAG = 1 << 4, - SCR_EA_FLAG = 1 << 3, - SCR_FIQ_FLAG = 1 << 2, - SCR_IRQ_FLAG = 1 << 1, - SCR_NS_FLAG = 1 << 0, -}; -CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0); -CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0); -CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1); -CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1); - -enum { - NSACR_NSTRCDIS_FLAG = 1 << 20, - NSACR_RFR_FLAG = 1 << 19, - NSACR_NSASEDIS = 1 << 15, - NSACR_NSD32DIS = 1 << 14, -#define NSACR_CP_FLAG(cp) (1 << cp) -}; -CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2); -CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2); - -/* Implemented as part of Virtualization extensions */ -CONTROL_REG_GEN_READ(HSCTLR, c1, 4, c0, 0); -CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0); -CONTROL_REG_GEN_READ(HACTLR, c1, 4, c0, 1); -CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1); - -CONTROL_REG_GEN_READ(HCR, c1, 4, c1, 0); -CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0); -CONTROL_REG_GEN_READ(HDCR, c1, 4, c1, 1); -CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1); -CONTROL_REG_GEN_READ(HCPTR, c1, 4, c1, 2); -CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2); -CONTROL_REG_GEN_READ(HSTR, c1, 4, c1, 3); -CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3); -CONTROL_REG_GEN_READ(HACR, c1, 4, c1, 7); -CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7); - -/* Memory protection and control registers */ -CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0); -CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0); -CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1); -CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1); -CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2); -CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2); - -CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2); -CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2); -CONTROL_REG_GEN_READ(VTCR, c2, 4, c1, 2); -CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2); - -/* PAE */ -CONTROL_REG_GEN_READ(TTBR0H, c2, 0, c2, 0); -CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0); -CONTROL_REG_GEN_READ(TTBR1H, c2, 0, c2, 1); -CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1); -CONTROL_REG_GEN_READ(HTTBRH, c2, 0, c2, 4); -CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4); -CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6); -CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6); - -CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0); -CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0); - -/* Memory system fault registers */ -CONTROL_REG_GEN_READ(DFSR, c5, 0, c0, 0); -CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0); -CONTROL_REG_GEN_READ(IFSR, c5, 0, c0, 1); -CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1); - -CONTROL_REG_GEN_READ(ADFSR, c5, 0, c1, 0); -CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0); -CONTROL_REG_GEN_READ(AIFSR, c5, 0, c1, 1); -CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1); - -CONTROL_REG_GEN_READ(HADFSR, c5, 4, c1, 0); -CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0); -CONTROL_REG_GEN_READ(HAIFSR, c5, 4, c1, 1); -CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1); -CONTROL_REG_GEN_READ(HSR, c5, 4, c2, 0); -CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0); - -CONTROL_REG_GEN_READ(DFAR, c6, 0, c0, 0); -CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0); -CONTROL_REG_GEN_READ(IFAR, c6, 0, c0, 2); -CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2); - -CONTROL_REG_GEN_READ(HDFAR, c6, 4, c0, 0); -CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0); -CONTROL_REG_GEN_READ(HIFAR, c6, 4, c0, 2); -CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2); -CONTROL_REG_GEN_READ(HPFAR, c6, 4, c0, 4); -CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4); - -/* Cache maintenance, address translation and other */ -CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */ -CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0); -CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6); -CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0); -CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); -CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */ -CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */ -CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0); -CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1); -CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4); -CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6); -CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7); - -CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1); -CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2); - -CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); -CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); -CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); -CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); -CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4); -CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5); -CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6); -CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7); - - -CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1); -CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2); -CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4); -CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5); -CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1); - -CONTROL_REG_GEN_WRITE(PFI, c7, 0, c11, 1); /* armv6 only */ - -CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1); -CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2); - -CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); -CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); - -/* TLB maintenance */ -CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */ -CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */ -CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */ -CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */ - -CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0); -CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1); -CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2); - -CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0); -CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1); -CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2); - -CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0); -CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1); -CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2); -CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3); - -CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */ -CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */ -CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */ - -CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0); -CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1); -CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4); - -/* c9 are performance monitoring resgisters */ -enum { - PMCR_IMP_MASK = 0xff, - PMCR_IMP_SHIFT = 24, - PMCR_IDCODE_MASK = 0xff, - PMCR_IDCODE_SHIFT = 16, - PMCR_EVENT_NUM_MASK = 0x1f, - PMCR_EVENT_NUM_SHIFT = 11, - PMCR_DP_FLAG = 1 << 5, - PMCR_X_FLAG = 1 << 4, - PMCR_D_FLAG = 1 << 3, - PMCR_C_FLAG = 1 << 2, - PMCR_P_FLAG = 1 << 1, - PMCR_E_FLAG = 1 << 0, -}; -CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0); -CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0); -enum { - PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31, -#define PMCNTENSET_COUNTER_EN_FLAG(c) (1 << c) -}; -CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1); -CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1); -CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0); -CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0); - - -/*c10 has tons of reserved too */ -CONTROL_REG_GEN_READ(PRRR, c10, 0, c2, 0); /* no PAE */ -CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */ -CONTROL_REG_GEN_READ(MAIR0, c10, 0, c2, 0); /* PAE */ -CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */ -CONTROL_REG_GEN_READ(NMRR, c10, 0, c2, 1); /* no PAE */ -CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */ -CONTROL_REG_GEN_READ(MAIR1, c10, 0, c2, 1); /* PAE */ -CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */ - -CONTROL_REG_GEN_READ(AMAIR0, c10, 0, c3, 0); /* PAE */ -CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */ -CONTROL_REG_GEN_READ(AMAIR1, c10, 0, c3, 1); /* PAE */ -CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */ - -CONTROL_REG_GEN_READ(HMAIR0, c10, 4, c2, 0); -CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0); -CONTROL_REG_GEN_READ(HMAIR1, c10, 4, c2, 1); -CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1); - -CONTROL_REG_GEN_READ(HAMAIR0, c10, 4, c3, 0); -CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0); -CONTROL_REG_GEN_READ(HAMAIR1, c10, 4, c3, 1); -CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1); - -/* c11 is reserved for TCM and DMA */ - -/* Security extensions */ -CONTROL_REG_GEN_READ(VBAR, c12, 0, c0, 0); -CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0); -CONTROL_REG_GEN_READ(MVBAR, c12, 0, c0, 1); -CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1); - -CONTROL_REG_GEN_READ(ISR, c12, 0, c1, 0); - -CONTROL_REG_GEN_READ(HVBAR, c12, 4, c0, 0); -CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0); - -/* Process context and thread id (FCSE) */ -CONTROL_REG_GEN_READ(FCSEIDR, c13, 0, c0, 0); - -CONTROL_REG_GEN_READ(CONTEXTIDR, c13, 0, c0, 1); -CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1); -CONTROL_REG_GEN_READ(TPIDRURW, c13, 0, c0, 2); -CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2); -CONTROL_REG_GEN_READ(TPIDRURO, c13, 0, c0, 3); -CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3); -CONTROL_REG_GEN_READ(TPIDRPRW, c13, 0, c0, 4); -CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4); - -CONTROL_REG_GEN_READ(HTPIDR, c13, 4, c0, 2); -CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2); - -/* Generic Timer Extensions */ -CONTROL_REG_GEN_READ(CNTFRQ, c14, 0, c0, 0); -CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0); -CONTROL_REG_GEN_READ(CNTKCTL, c14, 0, c1, 0); -CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0); - -CONTROL_REG_GEN_READ(CNTP_TVAL, c14, 0, c2, 0); -CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0); -CONTROL_REG_GEN_READ(CNTP_CTL, c14, 0, c2, 1); -CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1); - -CONTROL_REG_GEN_READ(CNTV_TVAL, c14, 0, c3, 0); -CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0); -CONTROL_REG_GEN_READ(CNTV_CTL, c14, 0, c3, 1); -CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1); - -CONTROL_REG_GEN_READ(CNTHCTL, c14, 4, c1, 0); -CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0); - -CONTROL_REG_GEN_READ(CNTHP_TVAL, c14, 4, c2, 0); -CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0); -CONTROL_REG_GEN_READ(CNTHP_CTL, c14, 4, c2, 1); -CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/cpu.h =================================================================== --- kernel/arch/arm32/include/cpu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,76 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief CPU identification. - */ - -#ifndef KERN_arm32_CPU_H_ -#define KERN_arm32_CPU_H_ - -#include -#include - -enum { - ARM_MAX_CACHE_LEVELS = 7, -}; - -/** Struct representing ARM CPU identification. */ -typedef struct { - /** Implementor (vendor) number. */ - uint32_t imp_num; - - /** Variant number. */ - uint32_t variant_num; - - /** Architecture number. */ - uint32_t arch_num; - - /** Primary part number. */ - uint32_t prim_part_num; - - /** Revision number. */ - uint32_t rev_num; - - struct { - unsigned ways; - unsigned sets; - unsigned line_size; - unsigned way_shift; - unsigned set_shift; - } dcache[ARM_MAX_CACHE_LEVELS]; - unsigned dcache_levels; -} cpu_arch_t; - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/cycle.h =================================================================== --- kernel/arch/arm32/include/cycle.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,67 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Count of CPU cycles. - */ - -#ifndef KERN_arm32_CYCLE_H_ -#define KERN_arm32_CYCLE_H_ - -#include -#include - -/** Return count of CPU cycles. - * - * No such instruction on ARM to get count of cycles. - * - * @return Count of CPU cycles. - * - */ -NO_TRACE static inline uint64_t get_cycle(void) -{ -#ifdef PROCESSOR_ARCH_armv7_a - if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) == - ID_PFR1_GEN_TIMER_EXT) { - uint32_t low = 0, high = 0; - asm volatile( "MRRC p15, 0, %[low], %[high], c14": [low]"=r"(low), [high]"=r"(high)); - return ((uint64_t)high << 32) | low; - } else { - return (uint64_t)PMCCNTR_read() * 64; - } -#endif - return 0; -} - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/elf.h =================================================================== --- kernel/arch/arm32/include/elf.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,52 +1,0 @@ -/* - * Copyright (c) 2006 Sergey Bondari - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief ARM ELF constants. - */ - -#ifndef KERN_arm32_ELF_H_ -#define KERN_arm32_ELF_H_ - -#define ELF_MACHINE EM_ARM - -#ifdef __BE__ - #define ELF_DATA_ENCODING ELFDATA2MSB -#else - #define ELF_DATA_ENCODING ELFDATA2LSB -#endif - -#define ELF_CLASS ELFCLASS32 - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/exception.h =================================================================== --- kernel/arch/arm32/include/exception.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,99 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt, Petr Stepan - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Exception declarations. - */ - -#ifndef KERN_arm32_EXCEPTION_H_ -#define KERN_arm32_EXCEPTION_H_ - -#include -#include - -/** If defined, forces using of high exception vectors. */ -#define HIGH_EXCEPTION_VECTORS - -#ifdef HIGH_EXCEPTION_VECTORS - #define EXC_BASE_ADDRESS 0xffff0000 -#else - #define EXC_BASE_ADDRESS 0x0 -#endif - -/* Exception Vectors */ -#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) -#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) -#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) -#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) -#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) -#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) -#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) - -/* Exception numbers */ -#define EXC_RESET 0 -#define EXC_UNDEF_INSTR 1 -#define EXC_SWI 2 -#define EXC_PREFETCH_ABORT 3 -#define EXC_DATA_ABORT 4 -#define EXC_IRQ 5 -#define EXC_FIQ 6 - -/** Kernel stack pointer. - * - * It is set when thread switches to user mode, - * and then used for exception handling. - * - */ -extern uintptr_t supervisor_sp; - -/** Temporary exception stack pointer. - * - * Temporary stack is used in exceptions handling routines - * before switching to thread's kernel stack. - * - */ -extern uintptr_t exc_stack; - -extern void install_exception_handlers(void); -extern void exception_init(void); -extern void reset_exception_entry(void); -extern void irq_exception_entry(void); -extern void fiq_exception_entry(void); -extern void undef_instr_exception_entry(void); -extern void prefetch_abort_exception_entry(void); -extern void data_abort_exception_entry(void); -extern void swi_exception_entry(void); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/faddr.h =================================================================== --- kernel/arch/arm32/include/faddr.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,51 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Function address conversion. - */ - -#ifndef KERN_arm32_FADDR_H_ -#define KERN_arm32_FADDR_H_ - -#include - -/** Calculate absolute address of function referenced by fptr pointer. - * - * @param fptr Function pointer. - * - */ -#define FADDR(fptr) ((uintptr_t) (fptr)) - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/fpu_context.h =================================================================== --- kernel/arch/arm32/include/fpu_context.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief FPU context. - */ - -#ifndef KERN_arm32_FPU_CONTEXT_H_ -#define KERN_arm32_FPU_CONTEXT_H_ - -#include - -#define FPU_CONTEXT_ALIGN 8 - -/* ARM Architecture reference manual, p B-1529. - */ -typedef struct { - uint32_t fpexc; - uint32_t fpscr; - uint32_t s[64]; -} fpu_context_t; - -void fpu_setup(void); - -bool handle_if_fpu_exception(void); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/interrupt.h =================================================================== --- kernel/arch/arm32/include/interrupt.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32interrupt - * @{ - */ -/** @file - * @brief Declarations of interrupt controlling routines. - */ - -#ifndef KERN_arm32_INTERRUPT_H_ -#define KERN_arm32_INTERRUPT_H_ - -#include -#include - -/** Initial size of exception dispatch table. */ -#define IVT_ITEMS 6 - -/** Index of the first item in exception dispatch table. */ -#define IVT_FIRST 0 - -extern void interrupt_init(void); -extern ipl_t interrupts_disable(void); -extern ipl_t interrupts_enable(void); -extern void interrupts_restore(ipl_t ipl); -extern ipl_t interrupts_read(void); -extern bool interrupts_disabled(void); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/istate.h =================================================================== --- kernel/arch/arm32/include/istate.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,105 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt, Petr Stepan - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32interrupt - * @{ - */ - -#ifndef KERN_arm32_ISTATE_H_ -#define KERN_arm32_ISTATE_H_ - -#include - -#ifdef KERNEL - -#include - -#else /* KERNEL */ - -#include - -#endif /* KERNEL */ - -/** Struct representing CPU state saved when an exception occurs. */ -typedef struct istate { - uint32_t dummy; - uint32_t spsr; - uint32_t sp; - uint32_t lr; - - uint32_t r0; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t fp; - uint32_t r12; - - uint32_t pc; -} istate_t; - -/** Set Program Counter member of given istate structure. - * - * @param istate istate structure - * @param retaddr new value of istate's PC member - * - */ -NO_TRACE static inline void istate_set_retaddr(istate_t *istate, - uintptr_t retaddr) -{ - istate->pc = retaddr; -} - -/** Return true if exception happened while in userspace. */ -NO_TRACE static inline int istate_from_uspace(istate_t *istate) -{ - return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; -} - -/** Return Program Counter member of given istate structure. */ -NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate) -{ - return istate->pc; -} - -NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate) -{ - return istate->fp; -} - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h =================================================================== --- kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup arm32beagleboardxm beagleboardxm - * @brief BeagleBoard-xM platform. - * @ingroup arm32 - * @{ - */ -/** @file - * @brief BeagleBoard platform driver. - */ - -#ifndef KERN_arm32_beagleboardxm_H_ -#define KERN_arm32_beagleboardxm_H_ - -#include - -extern struct arm_machine_ops bbxm_machine_ops; - -#endif - -/** @} - */ - Index: kernel/arch/arm32/include/mach/beaglebone/beaglebone.h =================================================================== --- kernel/arch/arm32/include/mach/beaglebone/beaglebone.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2012 Matteo Facchinetti - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup arm32beaglebone beaglebone - * @brief BeagleBone platform. - * @ingroup arm32 - * @{ - */ -/** @file - * @brief BeagleBone platform driver. - */ - -#ifndef KERN_arm32_beaglebone_H_ -#define KERN_arm32_beaglebone_H_ - -#include - -extern struct arm_machine_ops bbone_machine_ops; - -#endif - -/** @} - */ - Index: kernel/arch/arm32/include/mach/gta02/gta02.h =================================================================== --- kernel/arch/arm32/include/mach/gta02/gta02.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,51 +1,0 @@ -/* - * Copyright (c) 2010 Jiri Svoboda - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32gta02 GTA02 - * @brief Openmoko GTA02 platform. - * @ingroup arm32 - * @{ - */ -/** @file - * @brief Openmoko GTA02 platform driver. - */ - -#ifndef KERN_arm32_gta02_H_ -#define KERN_arm32_gta02_H_ - -#include - -extern struct arm_machine_ops gta02_machine_ops; - -/** Size of GTA02 IRQ number range (starting from 0) */ -#define GTA02_IRQ_COUNT 32 - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mach/integratorcp/integratorcp.h =================================================================== --- kernel/arch/arm32/include/mach/integratorcp/integratorcp.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,118 +1,0 @@ -/* - * Copyright (c) 2009 Vineeth Pillai - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32integratorcp - * @brief Integratorcp machine specific parts. - * @ingroup arm32 - * @{ - */ -/** @file - * @brief Integratorcp peripheries drivers declarations. - */ - -#ifndef KERN_arm32_icp_H_ -#define KERN_arm32_icp_H_ - -#include - -/** Last interrupt number (beginning from 0) whose status is probed - * from interrupt controller - */ -#define ICP_IRQC_MAX_IRQ 8 -#define ICP_KBD_IRQ 3 -#define ICP_TIMER_IRQ 6 - -/** Timer frequency */ -#define ICP_TIMER_FREQ 10000 - -#define ICP_UART 0x16000000 -#define ICP_KBD 0x18000000 -#define ICP_KBD_STAT 0x04 -#define ICP_KBD_DATA 0x08 -#define ICP_KBD_INTR_STAT 0x10 -#define ICP_RTC 0x13000000 -#define ICP_RTC1_LOAD_OFFSET 0x100 -#define ICP_RTC1_READ_OFFSET 0x104 -#define ICP_RTC1_CTL_OFFSET 0x108 -#define ICP_RTC1_INTRCLR_OFFSET 0x10C -#define ICP_RTC1_INTRSTAT_OFFSET 0x114 -#define ICP_RTC1_BGLOAD_OFFSET 0x118 -#define ICP_RTC_CTL_VALUE 0x00E2 -#define ICP_IRQC 0x14000000 -#define ICP_IRQC_MASK_OFFSET 0xC -#define ICP_IRQC_UNMASK_OFFSET 0x8 -#define ICP_FB 0x00800000 -#define ICP_FB_FRAME (ICP_FB >> 12) -#define ICP_FB_NUM_FRAME 512 -#define ICP_VGA 0xC0000000 -#define ICP_CMCR 0x10000000 -#define ICP_SDRAM_MASK 0x1C -#define ICP_SDRAMCR_OFFSET 0x20 - -typedef struct { - uintptr_t uart; - uintptr_t kbd_ctrl; - uintptr_t kbd_stat; - uintptr_t kbd_data; - uintptr_t kbd_intstat; - uintptr_t rtc; - uintptr_t rtc1_load; - uintptr_t rtc1_read; - uintptr_t rtc1_ctl; - uintptr_t rtc1_intrclr; - uintptr_t rtc1_intrstat; - uintptr_t rtc1_bgload; - uintptr_t irqc; - uintptr_t irqc_mask; - uintptr_t irqc_unmask; - uintptr_t vga; - uintptr_t cmcr; - uintptr_t sdramcr; -} icp_hw_map_t; - - -extern void icp_init(void); -extern void icp_output_init(void); -extern void icp_input_init(void); -extern void icp_timer_irq_start(void); -extern void icp_cpu_halt(void); -extern void icp_irq_exception(unsigned int, istate_t *); -extern void icp_get_memory_extents(uintptr_t *, size_t *); -extern void icp_frame_init(void); -extern size_t icp_get_irq_count(void); -extern const char *icp_get_platform_name(void); - -extern struct arm_machine_ops icp_machine_ops; - -/** Size of IntegratorCP IRQ number range (starting from 0) */ -#define ICP_IRQ_COUNT 8 - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/machine_func.h =================================================================== --- kernel/arch/arm32/include/machine_func.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,115 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * Copyright (c) 2009 Vineeth Pillai - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Declarations of machine specific functions. - * - * These functions enable to differentiate more kinds of ARM emulators - * or CPUs. It's the same concept as "arch" functions on the architecture - * level. - */ - -#ifndef KERN_arm32_MACHINE_FUNC_H_ -#define KERN_arm32_MACHINE_FUNC_H_ - -#include -#include -#include - -struct arm_machine_ops { - void (*machine_init)(void); - void (*machine_timer_irq_start)(void); - void (*machine_cpu_halt)(void); - void (*machine_get_memory_extents)(uintptr_t *, size_t *); - void (*machine_irq_exception)(unsigned int, istate_t *); - void (*machine_frame_init)(void); - void (*machine_output_init)(void); - void (*machine_input_init)(void); - size_t (*machine_get_irq_count)(void); - const char *(*machine_get_platform_name)(void); -}; - -/** Pointer to arm_machine_ops structure being used. */ -extern struct arm_machine_ops *machine_ops; - -/** Initialize machine_ops pointer. */ -extern void machine_ops_init(void); - -/** Maps HW devices to the kernel address space using #hw_map. */ -extern void machine_init(void); - - -/** Starts timer. */ -extern void machine_timer_irq_start(void); - - -/** Halts CPU. */ -extern void machine_cpu_halt(void); - -/** Get extents of available memory. - * - * @param start Place to store memory start address. - * @param size Place to store memory size. - */ -extern void machine_get_memory_extents(uintptr_t *start, size_t *size); - -/** Interrupt exception handler. - * - * @param exc_no Interrupt exception number. - * @param istate Saved processor state. - */ -extern void machine_irq_exception(unsigned int exc_no, istate_t *istate); - - -/* - * Machine specific frame initialization - */ -extern void machine_frame_init(void); - -/* - * configure the serial line output device. - */ -extern void machine_output_init(void); - -/* - * configure the serial line input device. - */ -extern void machine_input_init(void); - -extern size_t machine_get_irq_count(void); - -extern const char * machine_get_platform_name(void); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/as.h =================================================================== --- kernel/arch/arm32/include/mm/as.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,62 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief Address space manipulating functions declarations. - */ - -#ifndef KERN_arm32_AS_H_ -#define KERN_arm32_AS_H_ - -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 - -#define KERNEL_ADDRESS_SPACE_START_ARCH UINT32_C(0x80000000) -#define KERNEL_ADDRESS_SPACE_END_ARCH UINT32_C(0xffffffff) -#define USER_ADDRESS_SPACE_START_ARCH UINT32_C(0x00000000) -#define USER_ADDRESS_SPACE_END_ARCH UINT32_C(0x7fffffff) - -typedef struct { -} as_arch_t; - -#include - -#define as_constructor_arch(as, flags) (as != as) -#define as_destructor_arch(as) (as != as) -#define as_create_arch(as, flags) (as != as) -#define as_deinstall_arch(as) -#define as_invalidate_translation_cache(as, page, cnt) - -extern void as_arch_init(void); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/asid.h =================================================================== --- kernel/arch/arm32/include/mm/asid.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief ASIDs related declarations. - * - * ARM CPUs doesn't support ASIDs. - */ - -#ifndef KERN_arm32_ASID_H_ -#define KERN_arm32_ASID_H_ - -#include - -#define ASID_MAX_ARCH 3 /* minimal required number */ - -typedef uint8_t asid_t; - -/* - * This works due to fact that this file is never included alone but only - * through "generic/include/mm/asid.h" where ASID_START is defined. - */ -#define asid_get() (ASID_START + 1) - -#define asid_put(asid) - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/frame.h =================================================================== --- kernel/arch/arm32/include/mm/frame.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,83 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief Frame related declarations. - */ - -#ifndef KERN_arm32_FRAME_H_ -#define KERN_arm32_FRAME_H_ - -#define FRAME_WIDTH 12 /* 4KB frames */ -#define FRAME_SIZE (1 << FRAME_WIDTH) - -#ifndef __ASM__ - -#include - -#define BOOT_PAGE_TABLE_SIZE 0x4000 - -#ifdef MACHINE_gta02 - -#define PHYSMEM_START_ADDR 0x30008000 -#define BOOT_PAGE_TABLE_ADDRESS 0x30010000 - -#elif defined MACHINE_beagleboardxm - -#define PHYSMEM_START_ADDR 0x80000000 -#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 - -#elif defined MACHINE_beaglebone - -#define PHYSMEM_START_ADDR 0x80000000 -#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 - -#else - -#define PHYSMEM_START_ADDR 0x00000000 -#define BOOT_PAGE_TABLE_ADDRESS 0x00008000 - -#endif - -#define BOOT_PAGE_TABLE_START_FRAME (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH) -#define BOOT_PAGE_TABLE_SIZE_IN_FRAMES (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH) - -extern void frame_low_arch_init(void); -extern void frame_high_arch_init(void); -extern void boot_page_table_free(void); -#define physmem_print() - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/km.h =================================================================== --- kernel/arch/arm32/include/mm/km.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,57 +1,0 @@ -/* - * Copyright (c) 2011 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - */ - -#ifndef KERN_arm32_KM_H_ -#define KERN_arm32_KM_H_ - -#include - -#define KM_ARM32_IDENTITY_START UINT32_C(0x80000000) -#define KM_ARM32_IDENTITY_SIZE UINT32_C(0x70000000) - -#define KM_ARM32_NON_IDENTITY_START UINT32_C(0xf0000000) -/* - * The last virtual megabyte contains the high exception vectors (0xFFFF0000). - * Do not include this range into kernel non-identity. - */ -#define KM_ARM32_NON_IDENTITY_SIZE UINT32_C(0x0ff00000) - -extern void km_identity_arch_init(void); -extern void km_non_identity_arch_init(void); -extern bool km_is_non_identity_arch(uintptr_t); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,142 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief Paging related declarations. - */ - -#ifndef KERN_arm32_PAGE_H_ -#define KERN_arm32_PAGE_H_ - -#include -#include -#include -#include -#include - -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE - -#if (defined MACHINE_beagleboardxm) || (defined MACHINE_beaglebone) -#ifndef __ASM__ -# define KA2PA(x) ((uintptr_t) (x)) -# define PA2KA(x) ((uintptr_t) (x)) -#else -# define KA2PA(x) (x) -# define PA2KA(x) (x) -#endif -#else -#ifndef __ASM__ -# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) -# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) -#else -# define KA2PA(x) ((x) - 0x80000000) -# define PA2KA(x) ((x) + 0x80000000) -#endif -#endif - -/* Number of entries in each level. */ -#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ -#define PTL1_ENTRIES_ARCH 0 -#define PTL2_ENTRIES_ARCH 0 -/* coarse page tables used (256 * 4 = 1KB per page) */ -#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ - -/* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH FOUR_FRAMES -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME - -/* Macros calculating indices into page tables for each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) - -/* Get PTE address accessors for each level. */ -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ - ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ - (ptl1) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ - (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ - ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) - -/* Set PTE address accessors for each level. */ -#define SET_PTL0_ADDRESS_ARCH(ptl0) \ - (set_ptl0_addr((pte_t *) (ptl0))) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ - (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) -#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) -#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ - (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) - -/* Get PTE flags accessors for each level. */ -#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ - get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ - PAGE_PRESENT -#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ - PAGE_PRESENT -#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ - get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) - -/* Set PTE flags accessors for each level. */ -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ - set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) -#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) -#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ - set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x)) - -/* Set PTE present bit accessors for each level. */ -#define SET_PTL1_PRESENT_ARCH(ptl0, i) \ - set_pt_level0_present((pte_t *) (ptl0), (size_t) (i)) -#define SET_PTL2_PRESENT_ARCH(ptl1, i) -#define SET_PTL3_PRESENT_ARCH(ptl2, i) -#define SET_FRAME_PRESENT_ARCH(ptl3, i) \ - set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) - -#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a) -#include "page_armv6.h" -#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5) -#include "page_armv4.h" -#else -#error "Unsupported architecture" -#endif - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv4.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,269 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief Paging related declarations. - */ - -#ifndef KERN_arm32_PAGE_armv4_H_ -#define KERN_arm32_PAGE_armv4_H_ - -#ifndef KERN_arm32_PAGE_H_ -#error "Do not include arch specific page.h directly use generic page.h instead" -#endif - -/* Macros for querying the last-level PTE entries. */ -#define PTE_VALID_ARCH(pte) \ - (*((uint32_t *) (pte)) != 0) -#define PTE_PRESENT_ARCH(pte) \ - (((pte_t *) (pte))->l0.descriptor_type != 0) -#define PTE_GET_FRAME_ARCH(pte) \ - (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(pte) \ - (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) -#define PTE_EXECUTABLE_ARCH(pte) \ - 1 - -#ifndef __ASM__ - -/** Level 0 page table entry. */ -typedef struct { - /* 0b01 for coarse tables, see below for details */ - unsigned descriptor_type : 2; - unsigned impl_specific : 3; - unsigned domain : 4; - unsigned should_be_zero : 1; - - /* Pointer to the coarse 2nd level page table (holding entries for small - * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page - * tables that may hold even tiny pages (1KB) but they are bigger (4KB - * per table in comparison with 1KB per the coarse table) - */ - unsigned coarse_table_addr : 22; -} ATTRIBUTE_PACKED pte_level0_t; - -/** Level 1 page table entry (small (4KB) pages used). */ -typedef struct { - - /* 0b10 for small pages */ - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; - - /* access permissions for each of 4 subparts of a page - * (for each 1KB when small pages used */ - unsigned access_permission_0 : 2; - unsigned access_permission_1 : 2; - unsigned access_permission_2 : 2; - unsigned access_permission_3 : 2; - unsigned frame_base_addr : 20; -} ATTRIBUTE_PACKED pte_level1_t; - -typedef union { - pte_level0_t l0; - pte_level1_t l1; -} pte_t; - -/* Level 1 page tables access permissions */ - -/** User mode: no access, privileged mode: no access. */ -#define PTE_AP_USER_NO_KERNEL_NO 0 - -/** User mode: no access, privileged mode: read/write. */ -#define PTE_AP_USER_NO_KERNEL_RW 1 - -/** User mode: read only, privileged mode: read/write. */ -#define PTE_AP_USER_RO_KERNEL_RW 2 - -/** User mode: read/write, privileged mode: read/write. */ -#define PTE_AP_USER_RW_KERNEL_RW 3 - - -/* pte_level0_t and pte_level1_t descriptor_type flags */ - -/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_NOT_PRESENT 0 - -/** pte_level0_t coarse page table flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_COARSE_TABLE 1 - -/** pte_level1_t small page table flag (used in descriptor type). */ -#define PTE_DESCRIPTOR_SMALL_PAGE 2 - - -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} - - -/** Returns level 0 page table entry flags. - * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - - return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); -} - -/** Returns level 1 page table entry flags. - * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - int dt = p->descriptor_type; - int ap = p->access_permission_0; - - return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | - ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | - ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | - (p->bufferable << PAGE_CACHEABLE); -} - -/** Sets flags of level 0 page table entry. - * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - * - */ -NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) -{ - pte_level0_t *p = &pt[i].l0; - - if (flags & PAGE_NOT_PRESENT) { - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - /* - * Ensures that the entry will be recognized as valid when - * PTE_VALID_ARCH applied. - */ - p->should_be_zero = 1; - } else { - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; - p->should_be_zero = 0; - } -} - - -/** Sets flags of level 1 page table entry. - * - * We use same access rights for the whole page. When page - * is not preset we store 1 in acess_rigts_3 so that at least - * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - * - */ -NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) -{ - pte_level1_t *p = &pt[i].l1; - - if (flags & PAGE_NOT_PRESENT) - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - else - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; - - p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - - /* default access permission */ - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_NO_KERNEL_RW; - - if (flags & PAGE_USER) { - if (flags & PAGE_READ) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RO_KERNEL_RW; - } - if (flags & PAGE_WRITE) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RW_KERNEL_RW; - } - } -} - -NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - - p->should_be_zero = 0; - write_barrier(); - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; -} - - -NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; -} - - -extern void page_arch_init(void); - - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv6.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,285 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief Paging related declarations. - */ - -#ifndef KERN_arm32_PAGE_armv7_H_ -#define KERN_arm32_PAGE_armv7_H_ - -#ifndef KERN_arm32_PAGE_H_ -#error "Do not include arch specific page.h directly use generic page.h instead" -#endif - -/* Macros for querying the last-level PTE entries. */ -#define PTE_VALID_ARCH(pte) \ - (*((uint32_t *) (pte)) != 0) -#define PTE_PRESENT_ARCH(pte) \ - (((pte_t *) (pte))->l0.descriptor_type != 0) -#define PTE_GET_FRAME_ARCH(pte) \ - (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(pte) \ - (((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO) -#define PTE_EXECUTABLE_ARCH(pte) \ - (((pte_t *) (pte))->l1.descriptor_type != PTE_DESCRIPTOR_SMALL_PAGE_NX) - -#ifndef __ASM__ - -/** Level 0 page table entry. */ -typedef struct { - /* 0b01 for coarse tables, see below for details */ - unsigned descriptor_type : 2; - unsigned pxn : 1; - unsigned ns : 1; - unsigned should_be_zero_0 : 1; - unsigned domain : 4; - unsigned should_be_zero_1 : 1; - - /* Pointer to the coarse 2nd level page table (holding entries for small - * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page - * tables that may hold even tiny pages (1KB) but they are bigger (4KB - * per table in comparison with 1KB per the coarse table) - */ - unsigned coarse_table_addr : 22; -} ATTRIBUTE_PACKED pte_level0_t; - -/** Level 1 page table entry (small (4KB) pages used). */ -typedef struct { - - /* 0b10 for small pages, 0b11 for NX small pages */ - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; - unsigned access_permission_0 : 2; - unsigned tex : 3; - unsigned access_permission_1 : 1; - unsigned shareable : 1; - unsigned non_global : 1; - unsigned frame_base_addr : 20; -} ATTRIBUTE_PACKED pte_level1_t; - -typedef union { - pte_level0_t l0; - pte_level1_t l1; -} pte_t; - -/* Level 1 page tables access permissions */ - -/** User mode: no access, privileged mode: no access. */ -#define PTE_AP0_USER_NO_KERNEL_NO 0 - -/** User mode: no access, privileged mode: read/write. */ -#define PTE_AP0_USER_NO_KERNEL_FULL 1 - -/** User mode: read only, privileged mode: read/write. */ -#define PTE_AP0_USER_LIMITED_KERNEL_FULL 2 - -/** User mode: read/write, privileged mode: read/write. */ -#define PTE_AP0_USER_FULL_KERNEL_FULL 3 - -/** Allow writes */ -#define PTE_AP1_RO 1 - - -/* pte_level0_t and pte_level1_t descriptor_type flags */ - -/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_NOT_PRESENT 0 - -/** pte_level0_t coarse page table flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_COARSE_TABLE 1 - -/** pte_level1_t small page table flag (used in descriptor type). */ -#define PTE_DESCRIPTOR_SMALL_PAGE 2 - -/** pte_level1_t small page table flag with NX (used in descriptor type). */ -#define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 - -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} - - -/** Returns level 0 page table entry flags. - * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) -{ - const pte_level0_t *p = &pt[i].l0; - const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - - return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); -} - -/** Returns level 1 page table entry flags. - * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) -{ - const pte_level1_t *p = &pt[i].l1; - - const unsigned dt = p->descriptor_type; - const unsigned ap0 = p->access_permission_0; - const unsigned ap1 = p->access_permission_1; - - return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | - ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) | - ((ap0 == PTE_AP0_USER_LIMITED_KERNEL_FULL) << PAGE_READ_SHIFT) | - ((ap0 == PTE_AP0_USER_FULL_KERNEL_FULL) << PAGE_READ_SHIFT) | - ((ap0 == PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_READ_SHIFT) | - ((ap0 != PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_USER_SHIFT) | - (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_FULL_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | - (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_NO_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | - (p->bufferable << PAGE_CACHEABLE); -} - -/** Sets flags of level 0 page table entry. - * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - * - */ -NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) -{ - pte_level0_t *p = &pt[i].l0; - - if (flags & PAGE_NOT_PRESENT) { - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - /* - * Ensures that the entry will be recognized as valid when - * PTE_VALID_ARCH applied. - */ - p->should_be_zero_0 = 1; - p->should_be_zero_1 = 1; - } else { - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; - p->should_be_zero_0 = 0; - p->should_be_zero_1 = 0; - p->domain = 0; - p->ns = 0; - } -} - - -/** Sets flags of level 1 page table entry. - * - * We use same access rights for the whole page. When page - * is not preset we store 1 in acess_rigts_3 so that at least - * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - * - */ -NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) -{ - pte_level1_t *p = &pt[i].l1; - - if (flags & PAGE_NOT_PRESENT) { - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - } else { - if (flags & PAGE_EXEC) - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; - else - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; - } - - /* tex=0 buf=1 and cache=1 => normal memory - * tex=0 buf=1 and cache=0 => shareable device mmio - */ - p->cacheable = (flags & PAGE_CACHEABLE); - p->bufferable = 1; - p->tex = 0; - - /* Shareable is ignored for devices (non-cacheable), - * turn it on for normal memory. */ - p->shareable = 1; - - p->non_global = !(flags & PAGE_GLOBAL); - - /* default access permission: kernel only*/ - p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL; - - if (flags & PAGE_USER) { - p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL; - // TODO Fix kernel to use PAGE_WRITE flag properly and - // apply this for kernel pages as well. - if (!(flags & PAGE_WRITE)) - p->access_permission_1 = PTE_AP1_RO; - } -} - -NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - - p->should_be_zero_0 = 0; - p->should_be_zero_1 = 0; - write_barrier(); - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; -} - -NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; -} - - -extern void page_arch_init(void); - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/page_fault.h =================================================================== --- kernel/arch/arm32/include/mm/page_fault.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,105 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief Page fault related declarations. - */ - -#ifndef KERN_arm32_PAGE_FAULT_H_ -#define KERN_arm32_PAGE_FAULT_H_ - -#include - - -/** Decribes CP15 "fault status register" (FSR). - * - * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR. - * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of - * the architecture. A write flag (bit[11] of the DFSR) has also been - * introduced." - * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719) - * - * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). for FSR info - */ -typedef union { - struct { - unsigned status : 4; - unsigned domain : 4; - unsigned zero : 1; - unsigned lpae : 1; /**< Needs LPAE support implemented */ - unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */ - unsigned wr : 1; /**< armv6+ only */ - unsigned ext : 1 ; /**< external abort */ - unsigned cm : 1; /**< Cache maintenance, needs LPAE support */ - unsigned should_be_zero : 18; - } data; - struct { - unsigned status : 4; - unsigned sbz0 : 6; - unsigned fs : 1; - unsigned should_be_zero : 21; - } inst; - uint32_t raw; -} fault_status_t; - - -/** Simplified description of instruction code. - * - * @note Used for recognizing memory access instructions. - * @see ARM architecture reference (chapter 3.1) - */ -typedef struct { - unsigned dummy1 : 4; - unsigned bit4 : 1; - unsigned bits567 : 3; - unsigned dummy : 12; - unsigned access : 1; - unsigned opcode : 4; - unsigned type : 3; - unsigned condition : 4; -} ATTRIBUTE_PACKED instruction_t; - - -/** Help union used for casting pc register (uint_32_t) value into - * #instruction_t pointer. - */ -typedef union { - instruction_t *instr; - uint32_t pc; -} instruction_union_t; - -extern void prefetch_abort(unsigned int, istate_t *); -extern void data_abort(unsigned int, istate_t *); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/mm/tlb.h =================================================================== --- kernel/arch/arm32/include/mm/tlb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,42 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32mm - * @{ - */ -/** @file - * @brief TLB related declarations. - */ - -#ifndef KERN_arm32_TLB_H_ -#define KERN_arm32_TLB_H_ - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/proc/task.h =================================================================== --- kernel/arch/arm32/include/proc/task.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32proc - * @{ - */ -/** @file - * @brief Task related declarations. - */ - -#ifndef KERN_arm32_TASK_H_ -#define KERN_arm32_TASK_H_ - -typedef struct { -} task_arch_t; - -#define task_create_arch(t) -#define task_destroy_arch(t) - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/proc/thread.h =================================================================== --- kernel/arch/arm32/include/proc/thread.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,49 +1,0 @@ -/* - * Copyright (c) 2003-2004 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32proc - * @{ - */ -/** @file - * @brief Thread related declarations. - */ - -#ifndef KERN_arm32_THREAD_H_ -#define KERN_arm32_THREAD_H_ - -typedef struct { -} thread_arch_t; - -#define thr_constructor_arch(t) -#define thr_destructor_arch(t) -#define thread_create_arch(t) - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/ras.h =================================================================== --- kernel/arch/arm32/include/ras.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,53 +1,0 @@ -/* - * Copyright (c) 2009 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Declarations related to Restartable Atomic Sequences. - */ - -#ifndef KERN_arm32_RAS_H_ -#define KERN_arm32_RAS_H_ - -#include -#include - -#define RAS_START 0 -#define RAS_END 1 - -extern uintptr_t *ras_page; - -extern void ras_init(void); -extern void ras_check(unsigned int, istate_t *); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/regutils.h =================================================================== --- kernel/arch/arm32/include/regutils.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,91 +1,0 @@ -/* - * Copyright (c) 2007 Petr Stepan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** - * @file - * @brief Utilities for convenient manipulation with ARM registers. - */ - -#ifndef KERN_arm32_REGUTILS_H_ -#define KERN_arm32_REGUTILS_H_ - -#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) -#define STATUS_REG_MODE_MASK 0x1f - -/* ARM Processor Operation Modes */ -enum { - USER_MODE = 0x10, - FIQ_MODE = 0x11, - IRQ_MODE = 0x12, - SUPERVISOR_MODE = 0x13, - MONITOR_MODE = 0x16, - ABORT_MODE = 0x17, - HYPERVISOR_MODE = 0x1a, - UNDEFINED_MODE = 0x1b, - SYSTEM_MODE = 0x1f, - MODE_MASK = 0x1f, -}; -/* [CS]PRS manipulation macros */ -#define GEN_STATUS_READ(nm, reg) \ - static inline uint32_t nm## _status_reg_read(void) \ - { \ - uint32_t retval; \ - \ - asm volatile ( \ - "mrs %[retval], " #reg \ - : [retval] "=r" (retval) \ - ); \ - \ - return retval; \ - } - -#define GEN_STATUS_WRITE(nm, reg, fieldname, field) \ - static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ - { \ - asm volatile ( \ - "msr " #reg "_" #field ", %[value]" \ - :: [value] "r" (value) \ - ); \ - } - -/** Return the value of CPSR (Current Program Status Register). */ -GEN_STATUS_READ(current, cpsr); - -/** Set control bits of CPSR. */ -GEN_STATUS_WRITE(current, cpsr, control, c); - -/** Return the value of SPSR (Saved Program Status Register). */ -GEN_STATUS_READ(saved, spsr); - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/security_ext.h =================================================================== --- kernel/arch/arm32/include/security_ext.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,85 +1,0 @@ -/* - * Copyright (c) 2013 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Security Extensions Routines - */ - -#ifndef KERN_arm32_SECURITY_EXT_H_ -#define KERN_arm32_SECURITY_EXT_H_ - -#include -#include - -/** Test whether the current cpu supports security extensions. - * return true if security extensions are supported, false otherwise. - * @note The Processor Feature Register 1 that provides this information - * is available only on armv7+. This function returns false on all\ - * older archs. - */ -static inline bool sec_ext_is_implemented() -{ -#ifdef PROCESSOR_ARCH_armv7_a - const uint32_t idpfr = ID_PFR1_read() & ID_PFR1_SEC_EXT_MASK; - return idpfr == ID_PFR1_SEC_EXT || idpfr == ID_PFR1_SEC_EXT_RFR; -#endif - return false; -} - -/** Test whether we are running in monitor mode. - * return true, if the current mode is Monitor mode, false otherwise. - * @note this is safe to call even on machines that do not implement monitor - * mode. - */ -static inline bool sec_ext_is_monitor_mode() -{ - return (current_status_reg_read() & MODE_MASK) == MONITOR_MODE; -} - -/** Test whether we are running in a secure state. - * return true if the current state is secure, false otherwise. - * - * @note: This functions will cause undef isntruction trap if we - * are not running in the secure state. - * - * @note: u-boot enables non-secure access to cp 10/11, as well as some other - * features and switches to non-secure state during boot. - * Look for 'secureworld_exit' in arch/arm/cpu/armv7/omap3/board.c. - */ -static inline bool sec_ext_is_secure() -{ - return sec_ext_is_implemented() - && (sec_ext_is_monitor_mode() || !(SCR_read() & SCR_NS_FLAG)); -} - -#endif -/** @} - */ Index: kernel/arch/arm32/include/stack.h =================================================================== --- kernel/arch/arm32/include/stack.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,49 +1,0 @@ -/* - * Copyright (c) 2007 Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Stack constants. - */ - -#ifndef KERN_arm32_STACK_H_ -#define KERN_arm32_STACK_H_ - -#define STACK_ITEM_SIZE 4 - -/** See ABI for - * details - */ -#define STACK_ALIGNMENT 8 - -#endif - -/** @} - */ Index: kernel/arch/arm32/include/types.h =================================================================== --- kernel/arch/arm32/include/types.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,71 +1,0 @@ -/* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup arm32 - * @{ - */ -/** @file - * @brief Type definitions. - */ - -#ifndef KERN_arm32_TYPES_H_ -#define KERN_arm32_TYPES_H_ - -#ifndef DOXYGEN - #define ATTRIBUTE_PACKED __attribute__((packed)) -#else - #define ATTRIBUTE_PACKED -#endif - -typedef uint32_t size_t; -typedef int32_t ssize_t; - -typedef uint32_t uintptr_t; -typedef uint32_t pfn_t; - -typedef uint32_t ipl_t; - -typedef uint32_t sysarg_t; -typedef int32_t native_t; -typedef uint32_t atomic_count_t; - -typedef struct { -} fncptr_t; - -#define INTN_C(c) INT32_C(c) -#define UINTN_C(c) UINT32_C(c) - -#define PRIdn PRId32 /**< Format for native_t. */ -#define PRIun PRIu32 /**< Format for sysarg_t. */ -#define PRIxn PRIx32 /**< Format for hexadecimal sysarg_t. */ -#define PRIua PRIu32 /**< Format for atomic_count_t. */ - -#endif - -/** @} - */