Changeset 850235d in mainline for boot


Ignore:
Timestamp:
2013-03-10T14:56:21Z (13 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
05bab88
Parents:
ea906c29 (diff), 2277e03 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes

Location:
boot
Files:
12 edited

Legend:

Unmodified
Added
Removed

  • boot/Makefile.common

    rea906c29 r850235d  
    109109        $(USPACE_PATH)/srv/fs/exfat/exfat \
    110110        $(USPACE_PATH)/srv/fs/udf/udf \
    111         $(USPACE_PATH)/srv/fs/ext2fs/ext2fs \
    112111        $(USPACE_PATH)/srv/fs/ext4fs/ext4fs \
    113112        $(USPACE_PATH)/srv/hid/remcons/remcons \
    … …  
    167166        $(USPACE_PATH)/app/dload/dload \
    168167        $(USPACE_PATH)/app/edit/edit \
    169         $(USPACE_PATH)/app/ext2info/ext2info \
    170168        $(USPACE_PATH)/app/inet/inet \
    171169        $(USPACE_PATH)/app/kill/kill \

  • boot/Makefile.uboot

    rea906c29 r850235d  
    4040
    4141$(POST_OUTPUT): $(BIN_OUTPUT)
    42         $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr 0x30008000 -saddr 0x30008000 $< $@
     42        $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) -ostype $(UIMAGE_OS) $< $@
    4343
    4444clean:

  • boot/arch/arm32/Makefile.inc

    rea906c29 r850235d  
    3030        BOOT_OUTPUT = image.boot
    3131        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
     32        LADDR = 0x30008000
     33        SADDR = 0x30008000
     34        POSTBUILD = Makefile.uboot
     35endif
     36
     37ifeq ($(MACHINE), $(filter $(MACHINE),beagleboardxm beaglebone))
     38        BOOT_OUTPUT = image.boot
     39        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
     40        LADDR = 0x80000000
     41        SADDR = 0x80000000
    3242        POSTBUILD = Makefile.uboot
    3343endif
    … …  
    3949BITS = 32
    4050ENDIANESS = LE
    41 EXTRA_CFLAGS = -march=armv4
     51EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
    4252
     53ifeq ($(MACHINE), gta02)
    4354RD_SRVS_ESSENTIAL += \
    4455        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
    45         $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
     56        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
     57endif
    4658
    47 RD_SRVS_NON_ESSENTIAL += \
    48         $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd
     59RD_DRVS += \
     60        infrastructure/rootamdm37x \
     61        fb/amdm37x_dispc \
     62        bus/usb/ehci \
     63        bus/usb/ohci \
     64        bus/usb/usbflbk \
     65        bus/usb/usbhub \
     66        bus/usb/usbhid \
     67        bus/usb/usbmast \
     68        bus/usb/usbmid
    4969
    5070SOURCES = \

  • boot/arch/arm32/_link.ld.in

    rea906c29 r850235d  
    1111        . = BOOT_BASE + 0x8000;
    1212        .data : {
     13                bdata_start = .;
    1314                *(BOOTPT);      /* bootstrap page table */
    1415                *(BOOTSTACK);   /* bootstrap stack */
    … …  
    2425[[COMPONENTS]]
    2526        }
    26        
     27        bdata_end = .;
     28
    2729        /DISCARD/ : {
    2830                *(.gnu.*);

  • boot/arch/arm32/include/arch.h

    rea906c29 r850235d  
    4242#ifdef MACHINE_gta02
    4343#define BOOT_BASE       0x30008000
     44#elif defined MACHINE_beagleboardxm
     45#define BOOT_BASE       0x80000000
     46#elif defined MACHINE_beaglebone
     47#define BOOT_BASE       0x80000000
    4448#else
    4549#define BOOT_BASE       0x00000000
    … …  
    4852#define BOOT_OFFSET     (BOOT_BASE + 0xa00000)
    4953
     54#ifdef MACHINE_beagleboardxm
     55        #define PA_OFFSET 0
     56#elif defined MACHINE_beaglebone
     57        #define PA_OFFSET 0
     58#else
     59        #define PA_OFFSET 0x80000000
     60#endif
     61
    5062#ifndef __ASM__
    51         #define PA2KA(addr)  (((uintptr_t) (addr)) + 0x80000000)
     63        #define PA2KA(addr)  (((uintptr_t) (addr)) + PA_OFFSET)
    5264#else
    53         #define PA2KA(addr)  ((addr) + 0x80000000)
     65        #define PA2KA(addr)  ((addr) + PA_OFFSET)
    5466#endif
     67
    5568
    5669#endif

  • boot/arch/arm32/include/main.h

    rea906c29 r850235d  
    4040/** Address where characters to be printed are expected. */
    4141
     42
     43/** BeagleBoard-xM UART register address
     44 *
     45 * This is UART3 of AM/DM37x CPU
     46 */
     47#define BBXM_SCONS_THR          0x49020000
     48#define BBXM_SCONS_SSR          0x49020044
     49
     50/* Check this bit before writing (tx fifo full) */
     51#define BBXM_THR_FULL           0x00000001
     52
     53/** Beaglebone UART register addresses
     54 *
     55 * This is UART0 of AM335x CPU
     56 */
     57#define BBONE_SCONS_THR         0x44E09000
     58#define BBONE_SCONS_SSR         0x44E09044
     59
     60/** Check this bit before writing (tx fifo full) */
     61#define BBONE_TXFIFO_FULL       0x00000001
     62
    4263/** GTA02 serial console UART register addresses.
    4364 *
    … …  
    5172
    5273
    53 /** GXemul testarm serial console output register */
    54 #define TESTARM_SCONS_ADDR      0x10000000
    55 
    5674/** IntegratorCP serial console output register */
    5775#define ICP_SCONS_ADDR          0x16000000

  • boot/arch/arm32/include/mm.h

    rea906c29 r850235d  
    4747/** Describe "section" page table entry (one-level paging with 1 MB sized pages). */
    4848#define PTE_DESCRIPTOR_SECTION  0x02
     49/** Shift of memory address in section descriptor */
     50#define PTE_SECTION_SHIFT  20
    4951
    5052/** Page table access rights: user - no access, kernel - read/write. */
    5153#define PTE_AP_USER_NO_KERNEL_RW  0x01
     54
     55/** Start of memory mapped I/O area for GTA02 */
     56#define GTA02_IOMEM_START  0x48000000
     57/** End of memory mapped I/O area for GTA02 */
     58#define GTA02_IOMEM_END  0x60000000
     59
     60/** Start of ram memory on BBxM */
     61#define BBXM_RAM_START   0x80000000
     62/** Start of ram memory on BBxM */
     63#define BBXM_RAM_END   0xc0000000
     64
     65/** Start of ram memory on AM335x */
     66#define AM335x_RAM_START   0x80000000
     67/** End of ram memory on AM335x */
     68#define AM335x_RAM_END     0xC0000000
     69
    5270
    5371/* Page table level 0 entry - "section" format is used
    … …  
    5876        unsigned int bufferable : 1;
    5977        unsigned int cacheable : 1;
    60         unsigned int impl_specific : 1;
     78        unsigned int xn : 1;
    6179        unsigned int domain : 4;
    6280        unsigned int should_be_zero_1 : 1;
    63         unsigned int access_permission : 2;
    64         unsigned int should_be_zero_2 : 8;
     81        unsigned int access_permission_0 : 2;
     82        unsigned int tex : 3;
     83        unsigned int access_permission_1 : 1;
     84        unsigned int shareable : 1;
     85        unsigned int non_global : 1;
     86        unsigned int should_be_zero_2 : 1;
     87        unsigned int non_secure : 1;
    6588        unsigned int section_base_addr : 12;
    6689} __attribute__((packed)) pte_level0_section_t;

  • boot/arch/arm32/src/asm.S

    rea906c29 r850235d  
    6060        # before passing control to the copied code.
    6161        #
     62
     63        #
     64        # r0 is kernel entry point
     65        # r1 is pointer to the bootinfo structure
     66
     67#define CP15_C1_IC              12
     68#define CP15_C1_BP              11
     69#define CP15_C1_DC              2
     70        # Disable I-cache and D-cache before the kernel is started.
     71        mrc     p15, 0, r4, c1, c0, 0
     72        bic     r4, r4, #(1 << CP15_C1_DC)
     73        bic     r4, r4, #(1 << CP15_C1_IC)
     74        bic     r4, r4, #(1 << CP15_C1_BP)
     75        mcr     p15, 0, r4, c1, c0, 0
     76
     77       
     78        #Wait for the operations to complete
     79#ifdef PROCESSOR_ARCH_armv7_a
     80        dsb
     81#else
     82        #cp15 dsb, r4 is ignored (should be zero)
     83        mcr p15, 0, r4, c7, c10, 4
     84#endif
     85       
     86        # Clean ICache and BPredictors, r4 ignored (SBZ)
     87        mcr p15, 0, r4, c7, c5, 0
     88        nop
     89
     90        #Wait for the operations to complete
     91#ifdef PROCESSOR_ARCH_armv7_a
     92        isb
     93        nop
     94#else
     95        # cp15 isb
     96        mcr p15, 0, r4, c7, c5, 4
     97        nop
     98#endif
    6299        mov pc, r0

  • boot/arch/arm32/src/main.c

    rea906c29 r850235d  
    5050#define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
    5151
     52extern void *bdata_start;
     53extern void *bdata_end;
     54
     55
     56static inline void invalidate_icache(void)
     57{
     58        /* ICIALLU Invalidate entire ICache */
     59        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
     60}
     61
     62static inline void invalidate_dcache(void *address, size_t size)
     63{
     64        const uintptr_t addr = (uintptr_t)address;
     65        /* DCIMVAC - invalidate by address to the point of coherence */
     66        for (uintptr_t a = addr; a < addr + size; a += 4) {
     67                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
     68        }
     69}
     70
     71static inline void clean_dcache_poc(void *address, size_t size)
     72{
     73        const uintptr_t addr = (uintptr_t)address;
     74        /* DCCMVAC - clean by address to the point of coherence */
     75        for (uintptr_t a = addr; a < addr + size; a += 4) {
     76                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
     77        }
     78}
     79
    5280static bootinfo_t bootinfo;
    5381
    5482void bootstrap(void)
    5583{
     84        /* Make sure  we run in memory code when caches are enabled,
     85         * make sure we read memory data too. This part is ARMv7 specific as
     86         * ARMv7 no longer invalidates caches on restart.
     87         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
     88        invalidate_icache();
     89        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
     90
     91        /* Enable MMU and caches */
    5692        mmu_start();
    5793        version_print();
    5894       
     95        printf("Boot data: %p -> %p\n", &bdata_start, &bdata_end);
    5996        printf("\nMemory statistics\n");
    6097        printf(" %p|%p: bootstrap stack\n", &boot_stack, &boot_stack);
    … …  
    64101            (void *) PA2KA(BOOT_OFFSET), (void *) BOOT_OFFSET);
    65102       
    66         size_t i;
    67         for (i = 0; i < COMPONENTS; i++)
     103        for (size_t i = 0; i < COMPONENTS; i++) {
    68104                printf(" %p|%p: %s image (%u/%u bytes)\n", components[i].start,
    69105                    components[i].start, components[i].name, components[i].inflated,
    70106                    components[i].size);
     107                invalidate_dcache(components[i].start, components[i].size);
     108        }
    71109       
    72110        void *dest[COMPONENTS];
    … …  
    74112        size_t cnt = 0;
    75113        bootinfo.cnt = 0;
    76         for (i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
     114        for (size_t i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
    77115                top = ALIGN_UP(top, PAGE_SIZE);
    78116               
    … …  
    94132        printf("\nInflating components ... ");
    95133       
    96         for (i = cnt; i > 0; i--) {
     134        for (size_t i = cnt; i > 0; i--) {
    97135                void *tail = components[i - 1].start + components[i - 1].size;
    98136                if (tail >= dest[i - 1]) {
    … …  
    106144                int err = inflate(components[i - 1].start, components[i - 1].size,
    107145                    dest[i - 1], components[i - 1].inflated);
    108                
    109146                if (err != EOK) {
    110147                        printf("\n%s: Inflating error %d\n", components[i - 1].name, err);
    111148                        halt();
    112149                }
     150                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    113151        }
    114152       
    115153        printf(".\n");
    116154       
    117         printf("Booting the kernel... \n");
     155        printf("Booting the kernel...\n");
    118156        jump_to_kernel((void *) PA2KA(BOOT_OFFSET), &bootinfo);
    119157}

  • boot/arch/arm32/src/mm.c

    rea906c29 r850235d  
    3838#include <arch/mm.h>
    3939
     40/** Disable the MMU */
     41static void disable_paging(void)
     42{
     43        asm volatile (
     44                "mrc p15, 0, r0, c1, c0, 0\n"
     45                "bic r0, r0, #1\n"
     46                "mcr p15, 0, r0, c1, c0, 0\n"
     47                ::: "r0"
     48        );
     49}
     50
     51/** Check if caching can be enabled for a given memory section.
     52 *
     53 * Memory areas used for I/O are excluded from caching.
     54 * At the moment caching is enabled only on GTA02.
     55 *
     56 * @param section       The section number.
     57 *
     58 * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
     59*/
     60static inline int section_cacheable(pfn_t section)
     61{
     62#ifdef MACHINE_gta02
     63        unsigned long address = section << PTE_SECTION_SHIFT;
     64
     65        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
     66                return 0;
     67        else
     68                return 1;
     69#elif defined MACHINE_beagleboardxm
     70        const unsigned long address = section << PTE_SECTION_SHIFT;
     71        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
     72                return 1;
     73#elif defined MACHINE_beaglebone
     74        const unsigned long address = section << PTE_SECTION_SHIFT;
     75        if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
     76                return 1;
     77#endif
     78        return 0;
     79}
     80
    4081/** Initialize "section" page table entry.
    4182 *
    … …  
    5495{
    5596        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    56         pte->bufferable = 0;
    57         pte->cacheable = 0;
    58         pte->impl_specific = 0;
     97        pte->bufferable = 1;
     98        pte->cacheable = section_cacheable(frame);
     99        pte->xn = 0;
    59100        pte->domain = 0;
    60101        pte->should_be_zero_1 = 0;
    61         pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
     102        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
     103        pte->tex = 0;
     104        pte->access_permission_1 = 0;
     105        pte->shareable = 0;
     106        pte->non_global = 0;
    62107        pte->should_be_zero_2 = 0;
     108        pte->non_secure = 0;
    63109        pte->section_base_addr = frame;
    64110}
    … …  
    67113static void init_boot_pt(void)
    68114{
    69         pfn_t split_page = 0x800;
    70        
     115        const pfn_t split_page = PTL0_ENTRIES;
    71116        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    72117        pfn_t page;
    73118        for (page = 0; page < split_page; page++)
    74119                init_ptl0_section(&boot_pt[page], page);
    75        
    76         /*
    77          * Create 1:1 virtual-physical mapping in kernel space
    78          * (upper 2 GB), physical addresses start from 0.
    79          */
    80         for (page = split_page; page < PTL0_ENTRIES; page++)
    81                 init_ptl0_section(&boot_pt[page], page - split_page);
    82120       
    83121        asm volatile (
    … …  
    95133                /* Behave as a client of domains */
    96134                "ldr r0, =0x55555555\n"
    97                 "mcr p15, 0, r0, c3, c0, 0\n" 
    98                
     135                "mcr p15, 0, r0, c3, c0, 0\n"
     136
    99137                /* Current settings */
    100138                "mrc p15, 0, r0, c1, c0, 0\n"
    101139               
    102                 /* Mask to enable paging */
    103                 "ldr r1, =0x00000001\n"
     140                /* Enable ICache, DCache, BPredictors and MMU,
     141                 * we disable caches before jumping to kernel
     142                 * so this is safe for all archs.
     143                 */
     144                "ldr r1, =0x00001805\n"
     145               
    104146                "orr r0, r0, r1\n"
     147
     148                /* Invalidate the TLB content before turning on the MMU.
     149                 * ARMv7-A Reference manual, B3.10.3
     150                 */
     151                "mcr p15, 0, r0, c8, c7, 0\n"
    105152               
    106                 /* Store settings */
     153                /* Store settings, enable the MMU */
    107154                "mcr p15, 0, r0, c1, c0, 0\n"
    108155                ::: "r0", "r1"
    … …  
    112159/** Start the MMU - initialize page table and enable paging. */
    113160void mmu_start() {
     161        disable_paging();
    114162        init_boot_pt();
    115163        enable_paging();

  • boot/arch/arm32/src/putchar.c

    rea906c29 r850235d  
    4141#include <str.h>
    4242
     43#ifdef MACHINE_beaglebone
     44
     45/** Send a byte to the am335x serial console.
     46 *
     47 * @param byte          Byte to send.
     48 */
     49static void scons_sendb_bbone(uint8_t byte)
     50{
     51        volatile uint32_t *thr =
     52                (volatile uint32_t *) BBONE_SCONS_THR;
     53        volatile uint32_t *ssr =
     54                (volatile uint32_t *) BBONE_SCONS_SSR;
     55
     56        /* Wait until transmitter is empty */
     57        while (*ssr & BBONE_TXFIFO_FULL);
     58
     59        /* Transmit byte */
     60        *thr = (uint32_t) byte;
     61}
     62
     63#endif
     64
     65#ifdef MACHINE_beagleboardxm
     66
     67/** Send a byte to the amdm37x serial console.
     68 *
     69 * @param byte          Byte to send.
     70 */
     71static void scons_sendb_bbxm(uint8_t byte)
     72{
     73        volatile uint32_t *thr =
     74            (volatile uint32_t *)BBXM_SCONS_THR;
     75        volatile uint32_t *ssr =
     76            (volatile uint32_t *)BBXM_SCONS_SSR;
     77
     78        /* Wait until transmitter is empty. */
     79        while ((*ssr & BBXM_THR_FULL) == 1) ;
     80
     81        /* Transmit byte. */
     82        *thr = (uint32_t) byte;
     83}
     84
     85#endif
     86
    4387#ifdef MACHINE_gta02
    4488
    … …  
    65109#endif
    66110
    67 #ifdef MACHINE_testarm
    68 
    69 /** Send a byte to the GXemul testarm serial console.
    70  *
    71  * @param byte          Byte to send.
    72  */
    73 static void scons_sendb_testarm(uint8_t byte)
    74 {
    75         *((volatile uint8_t *) TESTARM_SCONS_ADDR) = byte;
    76 }
    77 
    78 #endif
    79 
    80111#ifdef MACHINE_integratorcp
    81112
    … …  
    97128static void scons_sendb(uint8_t byte)
    98129{
     130#ifdef MACHINE_beaglebone
     131        scons_sendb_bbone(byte);
     132#endif
     133#ifdef MACHINE_beagleboardxm
     134        scons_sendb_bbxm(byte);
     135#endif
    99136#ifdef MACHINE_gta02
    100137        scons_sendb_gta02(byte);
    101 #endif
    102 #ifdef MACHINE_testarm
    103         scons_sendb_testarm(byte);
    104138#endif
    105139#ifdef MACHINE_integratorcp

  • boot/arch/ia64/src/main.c

    rea906c29 r850235d  
    4848
    4949#define DEFAULT_MEMORY_BASE             0x4000000ULL
    50 #define DEFAULT_MEMORY_SIZE             0x4000000ULL
     50#define DEFAULT_MEMORY_SIZE             (256 * 1024 * 1024)
    5151#define DEFAULT_LEGACY_IO_BASE          0x00000FFFFC000000ULL
    5252#define DEFAULT_LEGACY_IO_SIZE          0x4000000ULL
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