Changes in kernel/arch/arm64/src/start.S [06f10ac:84176f3] in mainline
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kernel/arch/arm64/src/start.S (modified) (6 diffs)
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kernel/arch/arm64/src/start.S
r06f10ac r84176f3 35 35 .section K_TEXT_START, "ax" 36 36 37 .macro dcache_flush addr size temp0 temp138 mov \temp0, \addr39 mov \temp1, xzr40 41 0:42 /* Data or Unified Cache Line Clean */43 dc cvau, \temp044 add \temp0, \temp0, #445 add \temp1, \temp1, #446 cmp \temp1, \size47 blo 0b48 49 dsb ish50 isb51 .endm52 53 /** Kernel entry54 *55 * MMU must be disabled at this point.56 *57 * @param x0 Kernel entry point (kernel_image_start).58 * @param x1 Pointer to the bootinfo structure.59 *60 */61 37 SYMBOL(kernel_image_start) 38 /* 39 * Parameters: 40 * x0 is kernel entry point (kernel_image_start). 41 * x1 is pointer to the bootinfo structure. 42 * 43 * MMU must be disabled at this point. 44 */ 45 62 46 /* Get address of the main memory and remember it. */ 63 47 adrp x20, kernel_image_start - BOOT_OFFSET 64 48 adrp x2, physmem_base 49 /* add x2, x2, #:lo12:physmem_base */ 65 50 str x20, [x2] 66 51 67 /* Flush the data cache of physmem_base. */ 68 mov x28, #8 69 dcache_flush x2 x28 x29 x30 70 71 /* 72 * Set up address translation that identity maps the 1 GiB area that 52 /* 53 * Set up address translation that identity maps the gigabyte area that 73 54 * is holding the current execution page. 74 55 */ … … 95 76 mov x3, #( \ 96 77 1 << PTE_ACCESS_SHIFT | \ 97 MAIR_EL1_ NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \78 MAIR_EL1_DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 98 79 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 99 80 1 << PTE_PRESENT_SHIFT) … … 103 84 104 85 /* 105 * Set up address translation that maps the first 4 GiBof the kernel106 * identity virtual address space to the first 4 GiBof the physical86 * Set up address translation that maps the first gigabyte of the kernel 87 * identity virtual address space to the first gigabyte of the physical 107 88 * memory. 108 89 */ 109 90 110 91 mov x21, #KM_ARM64_IDENTITY_START 111 ldr x22, =(1024 * 1024 * 1024)112 92 113 93 /* Prepare the level 0 page table. */ … … 132 112 mov x3, #( \ 133 113 1 << PTE_ACCESS_SHIFT | \ 134 MAIR_EL1_ NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \114 MAIR_EL1_DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 135 115 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 136 116 1 << PTE_PRESENT_SHIFT) … … 138 118 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT 139 119 str x3, [x2] 140 141 /* 2nd GiB */142 add x23, x20, x22143 add x24, x21, x22144 145 adrp x2, upper_page_table_level1146 lsr x3, x24, #PTL1_VA_SHIFT147 and x3, x3, #PTL1_VA_MASK148 add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT149 mov x3, #( \150 1 << PTE_ACCESS_SHIFT | \151 MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \152 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \153 1 << PTE_PRESENT_SHIFT)154 lsr x4, x23, #FRAME_WIDTH155 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT156 str x3, [x2]157 158 /* 3rd GiB */159 add x23, x23, x22160 add x24, x24, x22161 162 adrp x2, upper_page_table_level1163 lsr x3, x24, #PTL1_VA_SHIFT164 and x3, x3, #PTL1_VA_MASK165 add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT166 mov x3, #( \167 1 << PTE_ACCESS_SHIFT | \168 MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \169 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \170 1 << PTE_PRESENT_SHIFT)171 lsr x4, x23, #FRAME_WIDTH172 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT173 str x3, [x2]174 175 /* 4th GiB */176 add x23, x23, x22177 add x24, x24, x22178 179 adrp x2, upper_page_table_level1180 lsr x3, x24, #PTL1_VA_SHIFT181 and x3, x3, #PTL1_VA_MASK182 add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT183 mov x3, #( \184 1 << PTE_ACCESS_SHIFT | \185 MAIR_EL1_DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \186 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \187 1 << PTE_PRESENT_SHIFT)188 lsr x4, x23, #FRAME_WIDTH189 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT190 str x3, [x2]191 192 /* Flush the data cache of page tables. */193 adrp x27, lower_page_table_level0194 mov x28, #4096195 dcache_flush x27 x28 x29 x30196 197 adrp x27, lower_page_table_level1198 mov x28, #4096199 dcache_flush x27 x28 x29 x30200 201 adrp x27, upper_page_table_level0202 mov x28, #4096203 dcache_flush x27 x28 x29 x30204 205 adrp x27, upper_page_table_level1206 mov x28, #4096207 dcache_flush x27 x28 x29 x30208 120 209 121 /* Make sure there are not any stale TLB entries. */ … … 359 271 lower_page_table_level0: 360 272 .space 4096 361 362 273 lower_page_table_level1: 363 274 .space 4096 364 365 275 upper_page_table_level0: 366 276 .space 4096 367 368 277 upper_page_table_level1: 369 278 .space 4096
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