Index: kernel/arch/sparc64/src/drivers/tick.c
===================================================================
--- kernel/arch/sparc64/src/drivers/tick.c	(revision aeaebcc155defcfcb8ff9cf60ddacb07fd8e84a7)
+++ kernel/arch/sparc64/src/drivers/tick.c	(revision 7f95cc5db47f3ff4bf23a7676c1ab43aecfb46df)
@@ -53,5 +53,6 @@
 	interrupt_register(14, "tick_int", tick_interrupt);
 	compare.int_dis = false;
-	compare.tick_cmpr = CPU->arch.clock_frequency/HZ;
+	compare.tick_cmpr = CPU->arch.clock_frequency / HZ;
+	CPU->arch.next_tick_cmpr = compare.tick_cmpr;
 	tick_compare_write(compare.value);
 	tick_write(0);
@@ -66,5 +67,5 @@
 {
 	softint_reg_t softint, clear;
-	uint64_t next, compare, start, stop;
+	uint64_t drift;
 	
 	softint.value = softint_read();
@@ -88,16 +89,18 @@
 	
 	/*
-	 * Restart counter.
+	 * Reprogram the compare register.
+	 * For now, we can ignore the potential of the registers to overflow.
+	 * On a 360MHz Ultra 60, the 63-bit compare counter will overflow in
+	 * about 812 years. If there was a 2GHz UltraSPARC computer, it would
+	 * overflow only in 146 years.
 	 */
-	compare = CPU->arch.clock_frequency/HZ;
-	start = tick_read();
-	next = start - compare;
-	while (next >= compare - TICK_RESTART_TIME) {
-		next -= compare;
+	drift = tick_read() - CPU->arch.next_tick_cmpr;
+	while (drift > CPU->arch.clock_frequency / HZ) {
+		drift -= CPU->arch.clock_frequency / HZ;
 		CPU->missed_clock_ticks++;
 	}
-	stop = tick_read();
-	tick_write(next + (stop - start));
-	
+	CPU->arch.next_tick_cmpr = tick_read() + (CPU->arch.clock_frequency / HZ)
+		- drift;
+	tick_compare_write(CPU->arch.next_tick_cmpr);
 	clock();
 }