Index: arch/mips32/include/arg.h
===================================================================
--- arch/mips32/include/arg.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/arg.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -43,5 +43,5 @@
  */
 
-typedef __address va_list;
+typedef uintptr_t va_list;
 
 #define va_start(ap, lst) \
@@ -49,5 +49,5 @@
 
 #define va_arg(ap, type)	\
-	(((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((__address)((ap) + 2*4 - 1) & (~3)) : ((__address)((ap) + 2*8 -1) & (~7)) )))[-1])
+	(((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((uintptr_t)((ap) + 2*4 - 1) & (~3)) : ((uintptr_t)((ap) + 2*8 -1) & (~7)) )))[-1])
 
 #define va_copy(dst,src) ((dst)=(src))
Index: arch/mips32/include/asm.h
===================================================================
--- arch/mips32/include/asm.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/asm.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -53,7 +53,7 @@
  * The stack must start on page boundary.
  */
-static inline __address get_stack_base(void)
+static inline uintptr_t get_stack_base(void)
 {
-	__address v;
+	uintptr_t v;
 	
 	__asm__ volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
@@ -63,7 +63,7 @@
 
 extern void cpu_halt(void);
-extern void asm_delay_loop(__u32 t);
-extern void userspace_asm(__address ustack, __address uspace_uarg,
-			  __address entry);
+extern void asm_delay_loop(uint32_t t);
+extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
+			  uintptr_t entry);
 
 #endif
Index: arch/mips32/include/boot.h
===================================================================
--- arch/mips32/include/boot.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/boot.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -35,10 +35,10 @@
 
 typedef struct {
-	__address addr;
-	__u32 size;
+	uintptr_t addr;
+	uint32_t size;
 } utask_t;
 
 typedef struct {
-	__u32 cnt;
+	uint32_t cnt;
 	utask_t tasks[TASKMAP_MAX_RECORDS];
 } bootinfo_t;
Index: arch/mips32/include/byteorder.h
===================================================================
--- arch/mips32/include/byteorder.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/byteorder.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -40,17 +40,17 @@
 
 #ifdef BIG_ENDIAN
-static inline __u64 __u64_le2host(__u64 n)
+static inline uint64_t uint64_t_le2host(uint64_t n)
 {
-	return __u64_byteorder_swap(n);
+	return uint64_t_byteorder_swap(n);
 }
 
-static inline __native __native_le2host(__native n)
+static inline unative_t unative_t_le2host(unative_t n)
 {
-	return __u32_byteorder_swap(n);
+	return uint32_t_byteorder_swap(n);
 }
 
 #else
-#  define __native_le2host(n)		(n)
-#  define __u64_le2host(n)		(n)
+#  define unative_t_le2host(n)		(n)
+#  define uint64_t_le2host(n)		(n)
 #endif
 
Index: arch/mips32/include/context.h
===================================================================
--- arch/mips32/include/context.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/context.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -56,17 +56,17 @@
  */
 struct context {
-	__address sp;
-	__address pc;
+	uintptr_t sp;
+	uintptr_t pc;
 	
-	__u32 s0;
-	__u32 s1;
-	__u32 s2;
-	__u32 s3;
-	__u32 s4;
-	__u32 s5;
-	__u32 s6;
-	__u32 s7;
-	__u32 s8;
-	__u32 gp;
+	uint32_t s0;
+	uint32_t s1;
+	uint32_t s2;
+	uint32_t s3;
+	uint32_t s4;
+	uint32_t s5;
+	uint32_t s6;
+	uint32_t s7;
+	uint32_t s8;
+	uint32_t gp;
 
 	ipl_t ipl;
Index: arch/mips32/include/cp0.h
===================================================================
--- arch/mips32/include/cp0.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/cp0.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -64,12 +64,12 @@
 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
-#define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
+#define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
   { \
-      __u32 retval; \
+      uint32_t retval; \
       asm("mfc0 %0, $" #reg : "=r"(retval)); \
       return retval; \
   }
 
-#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
+#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
  { \
     asm("mtc0 %0, $" #reg : : "r"(val) ); \
Index: arch/mips32/include/cpu.h
===================================================================
--- arch/mips32/include/cpu.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/cpu.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -39,6 +39,6 @@
 
 struct cpu_arch {
-	__u32 imp_num;
-	__u32 rev_num;
+	uint32_t imp_num;
+	uint32_t rev_num;
 };
 	
Index: arch/mips32/include/debugger.h
===================================================================
--- arch/mips32/include/debugger.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/debugger.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -51,7 +51,7 @@
 
 typedef struct  {
-	__address address;      /**< Breakpoint address */
-	__native instruction; /**< Original instruction */
-	__native nextinstruction;  /**< Original instruction following break */
+	uintptr_t address;      /**< Breakpoint address */
+	unative_t instruction; /**< Original instruction */
+	unative_t nextinstruction;  /**< Original instruction following break */
 	int flags;        /**< Flags regarding breakpoint */
 	count_t counter;
Index: arch/mips32/include/drivers/arc.h
===================================================================
--- arch/mips32/include/drivers/arc.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/drivers/arc.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -57,7 +57,7 @@
 
 typedef struct {
-	__u8 type;
-	__u8 sharedisposition;
-	__u16 flags;
+	uint8_t type;
+	uint8_t sharedisposition;
+	uint16_t flags;
 	union {
 		struct {
@@ -78,6 +78,6 @@
 
 typedef struct {
-	__u16 version;
-	__u16 revision;
+	uint16_t version;
+	uint16_t revision;
 	unsigned long count;
 	cm_resource_descriptor descr[1];
@@ -154,21 +154,21 @@
 	arc_component_type type;
 	arc_component_flags flags;
-	__u16 revision;
-	__u16 version;
-	__u32 key;
-	__u32 affinitymask;
-	__u32 configdatasize;
-	__u32 identifier_len;
+	uint16_t revision;
+	uint16_t version;
+	uint32_t key;
+	uint32_t affinitymask;
+	uint32_t configdatasize;
+	uint32_t identifier_len;
 	char *identifier;
 } __attribute__ ((packed)) arc_component;
 
 typedef struct {
-	__u16 year;
-	__u16 month;
-	__u16 day;
-	__u16 hour;
-	__u16 minutes;
-	__u16 seconds;
-	__u16 mseconds;
+	uint16_t year;
+	uint16_t month;
+	uint16_t day;
+	uint16_t hour;
+	uint16_t minutes;
+	uint16_t seconds;
+	uint16_t mseconds;
 } __attribute__ ((packed)) arc_timeinfo;
 
@@ -187,6 +187,6 @@
 typedef struct  {
 	arc_memorytype_t type;
-	__u32 basepage;  /* *4096 = baseaddr */
-	__u32 basecount;
+	uint32_t basepage;  /* *4096 = baseaddr */
+	uint32_t basecount;
 }arc_memdescriptor_t;
 
@@ -198,7 +198,7 @@
 typedef struct {
 	long (*load)(void); /* ... */
-	long (*invoke)(__u32 eaddr,__u32 saddr,__u32 argc,char **argv,
+	long (*invoke)(uint32_t eaddr,uint32_t saddr,uint32_t argc,char **argv,
 		       char **envp);
-	long (*execute)(char *path,__u32 argc,char **argv,char **envp);
+	long (*execute)(char *path,uint32_t argc,char **argv,char **envp);
 	void (*halt)(void);
 	void (*powerdown)(void);
@@ -222,11 +222,11 @@
 	long (*reserved2)(void);
 	arc_timeinfo * (*gettime)(void);
-	__u32 (*getrelativetime)(void);
+	uint32_t (*getrelativetime)(void);
 	long (*getdirectoryentry)();
 	long (*open)(void); /* ... */
-	long (*close)(__u32 fileid);
-	long (*read)(__u32 fileid,void *buf,__u32 n,__u32 *cnt);
-	long (*getreadstatus)(__u32 fileid);
-	long (*write)(__u32 fileid, void *buf,__u32 n,__u32 *cnt);
+	long (*close)(uint32_t fileid);
+	long (*read)(uint32_t fileid,void *buf,uint32_t n,uint32_t *cnt);
+	long (*getreadstatus)(uint32_t fileid);
+	long (*write)(uint32_t fileid, void *buf,uint32_t n,uint32_t *cnt);
 	long (*seek)(void); /* ... */
 /* 30 */
@@ -235,5 +235,5 @@
 	char * (*setenvironmentvariable)(char *name, char *value);
 	long (*getfileinformation)(void); /* ... */
-	long (*setfileinformation)(__u32 fileid,__u32 attflags,__u32 attmask);
+	long (*setfileinformation)(uint32_t fileid,uint32_t attflags,uint32_t attmask);
 	void (*flushallcaches)(void);
 	long (*testunicodecharacter)(void); /* ... */
@@ -242,17 +242,17 @@
 
 typedef struct {
-	__u32 signature;
-	__u32 length;
-	__u16 version;
-	__u16 revision;
+	uint32_t signature;
+	uint32_t length;
+	uint16_t version;
+	uint16_t revision;
 	void *restartblock;
 	void *debugblock;
 	void *gevector;
 	void *utlbmissvector;
-	__u32 firmwarevectorlen;
+	uint32_t firmwarevectorlen;
 	arc_func_vector_t *firmwarevector;
-	__u32 privvectorlen;
+	uint32_t privvectorlen;
 	void *privvector;
-	__u32 adaptercount;
+	uint32_t adaptercount;
 }__attribute__ ((packed)) arc_sbp;
 
Index: arch/mips32/include/exception.h
===================================================================
--- arch/mips32/include/exception.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/exception.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -63,43 +63,43 @@
 
 struct istate {
-	__u32 at;
-	__u32 v0;
-	__u32 v1;
-	__u32 a0;
-	__u32 a1;
-	__u32 a2;
-	__u32 a3;
-	__u32 t0;
-	__u32 t1;
-	__u32 t2;
-	__u32 t3;
-	__u32 t4;
-	__u32 t5;
-	__u32 t6;
-	__u32 t7;
-	__u32 s0;
-	__u32 s1;
-	__u32 s2;
-	__u32 s3;
-	__u32 s4;
-	__u32 s5;
-	__u32 s6;
-	__u32 s7;
-	__u32 t8;
-	__u32 t9;
-	__u32 gp;
-	__u32 sp;
-	__u32 s8;
-	__u32 ra;
+	uint32_t at;
+	uint32_t v0;
+	uint32_t v1;
+	uint32_t a0;
+	uint32_t a1;
+	uint32_t a2;
+	uint32_t a3;
+	uint32_t t0;
+	uint32_t t1;
+	uint32_t t2;
+	uint32_t t3;
+	uint32_t t4;
+	uint32_t t5;
+	uint32_t t6;
+	uint32_t t7;
+	uint32_t s0;
+	uint32_t s1;
+	uint32_t s2;
+	uint32_t s3;
+	uint32_t s4;
+	uint32_t s5;
+	uint32_t s6;
+	uint32_t s7;
+	uint32_t t8;
+	uint32_t t9;
+	uint32_t gp;
+	uint32_t sp;
+	uint32_t s8;
+	uint32_t ra;
 	
-	__u32 lo;
-	__u32 hi;
+	uint32_t lo;
+	uint32_t hi;
 
-	__u32 status; /* cp0_status */
-	__u32 epc; /* cp0_epc */
-	__u32 k1; /* We use it as thread-local pointer */
+	uint32_t status; /* cp0_status */
+	uint32_t epc; /* cp0_epc */
+	uint32_t k1; /* We use it as thread-local pointer */
 };
 
-static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
+static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
 {
 	istate->epc = retaddr;
@@ -111,5 +111,5 @@
 	return istate->status & cp0_status_um_bit;
 }
-static inline __native istate_get_pc(istate_t *istate)
+static inline unative_t istate_get_pc(istate_t *istate)
 {
 	return istate->epc;
Index: arch/mips32/include/faddr.h
===================================================================
--- arch/mips32/include/faddr.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/faddr.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -38,5 +38,5 @@
 #include <arch/types.h>
 
-#define FADDR(fptr)		((__address) (fptr))
+#define FADDR(fptr)		((uintptr_t) (fptr))
 
 #endif
Index: arch/mips32/include/fpu_context.h
===================================================================
--- arch/mips32/include/fpu_context.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/fpu_context.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -38,9 +38,9 @@
 #include <arch/types.h>
 
-#define FPU_CONTEXT_ALIGN    sizeof(__native)
+#define FPU_CONTEXT_ALIGN    sizeof(unative_t)
 
 struct fpu_context {
-	__native dregs[32];
-	__native cregs[32];
+	unative_t dregs[32];
+	unative_t cregs[32];
 };
 
Index: arch/mips32/include/memstr.h
===================================================================
--- arch/mips32/include/memstr.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/memstr.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -38,8 +38,8 @@
 #define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
 
-extern void memsetw(__address dst, size_t cnt, __u16 x);
-extern void memsetb(__address dst, size_t cnt, __u8 x);
+extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x);
+extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x);
 
-extern int memcmp(__address src, __address dst, int cnt);
+extern int memcmp(uintptr_t src, uintptr_t dst, int cnt);
 
 #endif
Index: arch/mips32/include/mm/asid.h
===================================================================
--- arch/mips32/include/mm/asid.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/mm/asid.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -40,5 +40,5 @@
 #define ASID_MAX_ARCH		255	/* 2^8 - 1 */
 
-typedef __u8 asid_t;
+typedef uint8_t asid_t;
 
 #endif
Index: arch/mips32/include/mm/page.h
===================================================================
--- arch/mips32/include/mm/page.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/mm/page.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -42,6 +42,6 @@
 
 #ifndef __ASM__
-#  define KA2PA(x)	(((__address) (x)) - 0x80000000)
-#  define PA2KA(x)	(((__address) (x)) + 0x80000000)
+#  define KA2PA(x)	(((uintptr_t) (x)) - 0x80000000)
+#  define PA2KA(x)	(((uintptr_t) (x)) + 0x80000000)
 #else
 #  define KA2PA(x)	((x) - 0x80000000)
@@ -101,5 +101,5 @@
 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)	set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
 
-#define PTE_VALID_ARCH(pte)			(*((__u32 *) (pte)) != 0)
+#define PTE_VALID_ARCH(pte)			(*((uint32_t *) (pte)) != 0)
 #define PTE_PRESENT_ARCH(pte)			((pte)->p != 0)
 #define PTE_GET_FRAME_ARCH(pte)			((pte)->pfn<<12)
Index: arch/mips32/include/mm/tlb.h
===================================================================
--- arch/mips32/include/mm/tlb.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/mm/tlb.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -76,5 +76,5 @@
 #endif
 	} __attribute__ ((packed));
-	__u32 value;
+	uint32_t value;
 };
 
@@ -104,5 +104,5 @@
 #endif
 	} __attribute__ ((packed));
-	__u32 value;
+	uint32_t value;
 };
 
@@ -119,5 +119,5 @@
 #endif
 	} __attribute__ ((packed));
-	__u32 value;
+	uint32_t value;
 };
 
@@ -134,5 +134,5 @@
 #endif
 	} __attribute__ ((packed));
-	__u32 value;
+	uint32_t value;
 };
 
Index: arch/mips32/include/types.h
===================================================================
--- arch/mips32/include/types.h	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/include/types.h	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -38,26 +38,26 @@
 #define NULL	0
 
-typedef signed char __s8;
-typedef unsigned char __u8;
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
 
-typedef signed short __s16;
-typedef unsigned short __u16;
+typedef signed short int16_t;
+typedef unsigned short uint16_t;
 
-typedef unsigned long __u32;
-typedef signed long __s32;
+typedef unsigned long uint32_t;
+typedef signed long int32_t;
 
-typedef unsigned long long __u64;
-typedef signed long long __s64;
+typedef unsigned long long uint64_t;
+typedef signed long long int64_t;
 
-typedef __u32 __address;
+typedef uint32_t uintptr_t;
 
-typedef __u32 ipl_t;
+typedef uint32_t ipl_t;
 
-typedef __u32 __native;
-typedef __s32 __snative;
+typedef uint32_t unative_t;
+typedef int32_t native_t;
 
 typedef struct pte pte_t;
 
-typedef __u32 pfn_t;
+typedef uint32_t pfn_t;
 
 #endif
Index: arch/mips32/src/ddi/ddi.c
===================================================================
--- arch/mips32/src/ddi/ddi.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/ddi/ddi.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -51,5 +51,5 @@
  * @return 0 on success or an error code from errno.h.
  */
-int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
+int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
 {
 	return 0;
Index: arch/mips32/src/debugger.c
===================================================================
--- arch/mips32/src/debugger.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/debugger.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -92,6 +92,6 @@
 
 static struct {
-	__u32 andmask;
-	__u32 value;
+	uint32_t andmask;
+	uint32_t value;
 }jmpinstr[] = {
 	{0xf3ff0000, 0x41000000}, /* BCzF */
@@ -126,5 +126,5 @@
  * @return true - it is jump instruction, false otherwise
  */
-static bool is_jump(__native instr)
+static bool is_jump(unative_t instr)
 {
 	int i;
@@ -154,10 +154,10 @@
 	/* Check, that the breakpoints do not conflict */
 	for (i=0; i<BKPOINTS_MAX; i++) {
-		if (breakpoints[i].address == (__address)argv->intval) {
+		if (breakpoints[i].address == (uintptr_t)argv->intval) {
 			printf("Duplicate breakpoint %d.\n", i);
 			spinlock_unlock(&bkpoints_lock);
 			return 0;
-		} else if (breakpoints[i].address == (__address)argv->intval + sizeof(__native) || \
-			   breakpoints[i].address == (__address)argv->intval - sizeof(__native)) {
+		} else if (breakpoints[i].address == (uintptr_t)argv->intval + sizeof(unative_t) || \
+			   breakpoints[i].address == (uintptr_t)argv->intval - sizeof(unative_t)) {
 			printf("Adjacent breakpoints not supported, conflict with %d.\n", i);
 			spinlock_unlock(&bkpoints_lock);
@@ -178,8 +178,8 @@
 		return 0;
 	}
-	cur->address = (__address) argv->intval;
+	cur->address = (uintptr_t) argv->intval;
 	printf("Adding breakpoint on address: %p\n", argv->intval);
-	cur->instruction = ((__native *)cur->address)[0];
-	cur->nextinstruction = ((__native *)cur->address)[1];
+	cur->instruction = ((unative_t *)cur->address)[0];
+	cur->nextinstruction = ((unative_t *)cur->address)[1];
 	if (argv == &add_argv) {
 		cur->flags = 0;
@@ -193,5 +193,5 @@
 
 	/* Set breakpoint */
-	*((__native *)cur->address) = 0x0d;
+	*((unative_t *)cur->address) = 0x0d;
 
 	spinlock_unlock(&bkpoint_lock);
@@ -229,6 +229,6 @@
 		return 0;
 	}
-	((__u32 *)cur->address)[0] = cur->instruction;
-	((__u32 *)cur->address)[1] = cur->nextinstruction;
+	((uint32_t *)cur->address)[0] = cur->instruction;
+	((uint32_t *)cur->address)[1] = cur->nextinstruction;
 
 	cur->address = NULL;
@@ -299,5 +299,5 @@
 {
 	bpinfo_t *cur = NULL;
-	__address fireaddr = istate->epc;
+	uintptr_t fireaddr = istate->epc;
 	int i;
 
@@ -316,5 +316,5 @@
 		/* Reinst only breakpoint */
 		if ((breakpoints[i].flags & BKPOINT_REINST) \
-		    && (fireaddr ==breakpoints[i].address+sizeof(__native))) {
+		    && (fireaddr ==breakpoints[i].address+sizeof(unative_t))) {
 			cur = &breakpoints[i];
 			break;
@@ -324,7 +324,7 @@
 		if (cur->flags & BKPOINT_REINST) {
 			/* Set breakpoint on first instruction */
-			((__u32 *)cur->address)[0] = 0x0d;
+			((uint32_t *)cur->address)[0] = 0x0d;
 			/* Return back the second */
-			((__u32 *)cur->address)[1] = cur->nextinstruction;
+			((uint32_t *)cur->address)[1] = cur->nextinstruction;
 			cur->flags &= ~BKPOINT_REINST;
 			spinlock_unlock(&bkpoint_lock);
@@ -339,9 +339,9 @@
 
 		/* Return first instruction back */
-		((__u32 *)cur->address)[0] = cur->instruction;
+		((uint32_t *)cur->address)[0] = cur->instruction;
 
 		if (! (cur->flags & BKPOINT_ONESHOT)) {
 			/* Set Breakpoint on next instruction */
-			((__u32 *)cur->address)[1] = 0x0d;
+			((uint32_t *)cur->address)[1] = 0x0d;
 			cur->flags |= BKPOINT_REINST;
 		} 
Index: arch/mips32/src/drivers/arc.c
===================================================================
--- arch/mips32/src/drivers/arc.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/drivers/arc.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -143,5 +143,5 @@
 		case CmResourceTypePort:
 			printf("Port: %p-size:%d ",
-			       (__address)configdata->descr[i].u.port.start,
+			       (uintptr_t)configdata->descr[i].u.port.start,
 			       configdata->descr[i].u.port.length);
 			break;
@@ -153,5 +153,5 @@
 		case CmResourceTypeMemory:
 			printf("Memory: %p-size:%d ",
-			       (__address)configdata->descr[i].u.port.start,
+			       (uintptr_t)configdata->descr[i].u.port.start,
 			       configdata->descr[i].u.port.length);
 			break;
@@ -237,5 +237,5 @@
 static void arc_putchar(char ch)
 {
-	__u32 cnt;
+	uint32_t cnt;
 	ipl_t ipl;
 
@@ -294,5 +294,5 @@
 {
 	char ch;
-	__u32 count;
+	uint32_t count;
 	long result;
 	
@@ -317,5 +317,5 @@
 {
 	char ch;
-	__u32 count;
+	uint32_t count;
 	long result;
 
@@ -381,5 +381,5 @@
 	arc_memdescriptor_t *desc;
 	int total = 0;
-	__address base;
+	uintptr_t base;
 	size_t basesize;
 
Index: arch/mips32/src/exception.c
===================================================================
--- arch/mips32/src/exception.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/exception.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -96,5 +96,5 @@
 static void reserved_instr_exception(int n, istate_t *istate)
 {
-	if (*((__u32 *)istate->epc) == 0x7c03e83b) {
+	if (*((uint32_t *)istate->epc) == 0x7c03e83b) {
 		ASSERT(THREAD);
 		istate->epc += 4;
@@ -140,5 +140,5 @@
 static void interrupt_exception(int n, istate_t *istate)
 {
-	__u32 cause;
+	uint32_t cause;
 	int i;
 	
Index: arch/mips32/src/interrupt.c
===================================================================
--- arch/mips32/src/interrupt.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/interrupt.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -133,5 +133,5 @@
 
 /* Reregister irq to be IPC-ready */
-void irq_ipc_bind_arch(__native irq)
+void irq_ipc_bind_arch(unative_t irq)
 {
 	/* Do not allow to redefine timer */
Index: arch/mips32/src/mips32.c
===================================================================
--- arch/mips32/src/mips32.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/mips32.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -72,5 +72,5 @@
  * when not in .text section ????????
  */
-__address supervisor_sp __attribute__ ((section (".text")));
+uintptr_t supervisor_sp __attribute__ ((section (".text")));
 /* Stack pointer saved when entering user mode */
 /* TODO: How do we do it on SMP system???? */
@@ -82,5 +82,5 @@
 	init.cnt = bootinfo.cnt;
 	
-	__u32 i;
+	uint32_t i;
 	
 	for (i = 0; i < bootinfo.cnt; i++) {
@@ -147,8 +147,8 @@
 					      cp0_status_um_bit |
 					      cp0_status_ie_enabled_bit));
-	cp0_epc_write((__address) kernel_uarg->uspace_entry);
-	userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), 
-		      (__address) kernel_uarg->uspace_uarg,
-		      (__address) kernel_uarg->uspace_entry);
+	cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
+	userspace_asm(((uintptr_t) kernel_uarg->uspace_stack+PAGE_SIZE), 
+		      (uintptr_t) kernel_uarg->uspace_uarg,
+		      (uintptr_t) kernel_uarg->uspace_entry);
 	while (1)
 		;
@@ -163,5 +163,5 @@
 void before_thread_runs_arch(void)
 {
-	supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
+	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
 }
 
@@ -175,5 +175,5 @@
  * possible to have it separately in the future.
  */
-__native sys_tls_set(__native addr)
+unative_t sys_tls_set(unative_t addr)
 {
 	return 0;
Index: arch/mips32/src/mm/page.c
===================================================================
--- arch/mips32/src/mm/page.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/mm/page.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -46,5 +46,5 @@
  *   translate the physical address to uncached area
  */
-__address hw_map(__address physaddr, size_t size)
+uintptr_t hw_map(uintptr_t physaddr, size_t size)
 {
 	return physaddr + 0xa0000000;
Index: arch/mips32/src/mm/tlb.c
===================================================================
--- arch/mips32/src/mm/tlb.c	(revision a6dd361b1b93be3250db112f36c9db227c077ff9)
+++ arch/mips32/src/mm/tlb.c	(revision 7f1c620c9e5bd00a90322b5118b47b8b033b5152)
@@ -52,8 +52,8 @@
 static void tlb_modified_fail(istate_t *istate);
 
-static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc);
-
-static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
-static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
+static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
+
+static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
+static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
 
 /** Initialize TLB
@@ -97,5 +97,5 @@
 	entry_hi_t hi;
 	asid_t asid;
-	__address badvaddr;
+	uintptr_t badvaddr;
 	pte_t *pte;
 	int pfrc;
@@ -167,5 +167,5 @@
 {
 	tlb_index_t index;
-	__address badvaddr;
+	uintptr_t badvaddr;
 	entry_lo_t lo;
 	entry_hi_t hi;
@@ -251,5 +251,5 @@
 {
 	tlb_index_t index;
-	__address badvaddr;
+	uintptr_t badvaddr;
 	entry_lo_t lo;
 	entry_hi_t hi;
@@ -384,5 +384,5 @@
  * @return PTE on success, NULL otherwise.
  */
-pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc)
+pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
 {
 	entry_hi_t hi;
@@ -446,5 +446,5 @@
 }
 
-void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
+void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
 {
 	lo->value = 0;
@@ -456,5 +456,5 @@
 }
 
-void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
+void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
 {
 	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
@@ -568,5 +568,5 @@
  * @param cnt Number of entries to invalidate.
  */
-void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
+void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
 {
 	int i;