Index: kernel/arch/arm32/include/arch/cp15.h
===================================================================
--- kernel/arch/arm32/include/arch/cp15.h	(revision af69a4ba72b68409f26d6a65f6f60ac426247b42)
+++ kernel/arch/arm32/include/arch/cp15.h	(revision 7ec3c5638215716bb0cffafe64b4b0bdc6a543b3)
@@ -47,5 +47,5 @@
 
 #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
-static inline uint32_t name##_read() \
+static inline uint32_t name##_read(void) \
 { \
 	uint32_t val; \
Index: kernel/arch/arm32/include/arch/security_ext.h
===================================================================
--- kernel/arch/arm32/include/arch/security_ext.h	(revision af69a4ba72b68409f26d6a65f6f60ac426247b42)
+++ kernel/arch/arm32/include/arch/security_ext.h	(revision 7ec3c5638215716bb0cffafe64b4b0bdc6a543b3)
@@ -46,5 +46,5 @@
  * older archs.
  */
-static inline bool sec_ext_is_implemented()
+static inline bool sec_ext_is_implemented(void)
 {
 #ifdef PROCESSOR_ARCH_armv7_a
@@ -60,5 +60,5 @@
  * mode.
  */
-static inline bool sec_ext_is_monitor_mode()
+static inline bool sec_ext_is_monitor_mode(void)
 {
 	return (current_status_reg_read() & MODE_MASK) == MONITOR_MODE;
@@ -75,5 +75,5 @@
  * Look for 'secureworld_exit' in arch/arm/cpu/armv7/omap3/board.c.
  */
-static inline bool sec_ext_is_secure()
+static inline bool sec_ext_is_secure(void)
 {
 	return sec_ext_is_implemented()
Index: kernel/arch/arm32/src/arm32.c
===================================================================
--- kernel/arch/arm32/src/arm32.c	(revision af69a4ba72b68409f26d6a65f6f60ac426247b42)
+++ kernel/arch/arm32/src/arm32.c	(revision 7ec3c5638215716bb0cffafe64b4b0bdc6a543b3)
@@ -158,5 +158,5 @@
 
 /** Reboot. */
-void arch_reboot()
+void arch_reboot(void)
 {
 	/* not implemented */
Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision af69a4ba72b68409f26d6a65f6f60ac426247b42)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 7ec3c5638215716bb0cffafe64b4b0bdc6a543b3)
@@ -101,4 +101,5 @@
 	FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
 };
+
 extern uint32_t fpscr_read(void);
 extern void fpscr_write(uint32_t);
@@ -114,7 +115,8 @@
 static void (*restore_context)(fpu_context_t *ctx);
 
-static int fpu_have_coprocessor_access()
-{
-/* The register containing the information (CPACR) is not available on armv6-
+static int fpu_have_coprocessor_access(void)
+{
+/*
+ * The register containing the information (CPACR) is not available on armv6-
  * rely on user decision to use CONFIG_FPU.
  */
@@ -143,7 +145,8 @@
  * @note do we need to call secure monitor here?
  */
-static void fpu_enable_coprocessor_access()
-{
-/* The register containing the information (CPACR) is not available on armv6-
+static void fpu_enable_coprocessor_access(void)
+{
+/*
+ * The register containing the information (CPACR) is not available on armv6-
  * rely on user decision to use CONFIG_FPU.
  */