Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 7290ca0c7924417e4d8915bf1601248a8ffc3a0f)
+++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 7eb49f453d96a8927bbed46671d19a9561e355ea)
@@ -153,6 +153,20 @@
 	assert(clock_control_cm);
 
-	/* Always set DPLL5 to automatic */
-	uint32_t reg = clock_control_cm->autoidle2_pll;
+	uint32_t reg;
+
+	/* Set DPLL3 and DPLL4 to automatic */
+	reg = clock_control_cm->autoidle_pll;
+	reg &= ~(CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK <<
+	    CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_SHIFT);
+	reg &= ~(CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK <<
+	    CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_SHIFT);
+	reg |= (CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC <<
+	    CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_SHIFT);
+	reg |= (CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC <<
+	    CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_SHIFT);
+	clock_control_cm->autoidle_pll = reg;
+
+	/* Set DPLL5 to automatic */
+	reg = clock_control_cm->autoidle2_pll;
 	reg &= ~(CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK <<
 	    CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_SHIFT);
@@ -160,4 +174,5 @@
 	    CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_SHIFT);
 	clock_control_cm->autoidle2_pll = reg;
+
 
 #ifdef DEBUG_CM