Index: kernel/arch/abs32le/include/mm/page.h
===================================================================
--- kernel/arch/abs32le/include/mm/page.h	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/abs32le/include/mm/page.h	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -105,4 +105,12 @@
 	set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
 
+/* Set PTE present bit accessors for each level. */
+#define SET_PTL1_PRESENT_ARCH(ptl0, i)	\
+	set_pt_present((pte_t *) (ptl0), (size_t) (i))
+#define SET_PTL2_PRESENT_ARCH(ptl1, i)
+#define SET_PTL3_PRESENT_ARCH(ptl2, i)
+#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
+	set_pt_present((pte_t *) (ptl3), (size_t) (i))
+
 /* Macros for querying the last level entries. */
 #define PTE_VALID_ARCH(p) \
@@ -173,4 +181,13 @@
 }
 
+NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+    WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH))
+    REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)
+{
+	pte_t *p = &pt[i];
+
+	p->present = 1;
+}
+
 extern void page_arch_init(void);
 extern void page_fault(unsigned int, istate_t *);
Index: kernel/arch/amd64/include/mm/page.h
===================================================================
--- kernel/arch/amd64/include/mm/page.h	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/amd64/include/mm/page.h	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -119,4 +119,14 @@
 	set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
 
+/* Set PTE present bit accessors for each level. */
+#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
+	set_pt_present((pte_t *) (ptl0), (size_t) (i))
+#define SET_PTL2_PRESENT_ARCH(ptl1, i) \
+	set_pt_present((pte_t *) (ptl1), (size_t) (i))
+#define SET_PTL3_PRESENT_ARCH(ptl2, i) \
+	set_pt_present((pte_t *) (ptl2), (size_t) (i))
+#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
+	set_pt_present((pte_t *) (ptl3), (size_t) (i))
+
 /* Macros for querying the last-level PTE entries. */
 #define PTE_VALID_ARCH(p) \
@@ -215,4 +225,11 @@
 }
 
+NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+{
+	pte_t *p = &pt[i];
+
+	p->present = 1;
+}
+
 extern void page_arch_init(void);
 extern void page_fault(unsigned int, istate_t *);
Index: kernel/arch/amd64/src/asm.S
===================================================================
--- kernel/arch/amd64/src/asm.S	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/amd64/src/asm.S	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -362,5 +362,13 @@
 	 */
 	call syscall_handler
-	
+
+	/*
+	 * Test if the saved return address is canonical and not-kernel.
+	 * We do this by looking at the 16 most significant bits
+	 * of the saved return address (two bytes at offset 6).
+	 */
+	testw $0xffff, ISTATE_OFFSET_RIP+6(%rsp)
+	jnz bad_rip 
+
 	cli
 	
@@ -388,4 +396,14 @@
 	sysretq
 
+bad_rip:
+	movq %rsp, %rdi
+	movabs $bad_rip_msg, %rsi
+	xorb %al, %al
+	callq fault_from_uspace
+	/* not reached */
+	
+bad_rip_msg:
+	.asciz "Invalid instruction pointer."
+
 /** Print Unicode character to EGA display.
  *
Index: kernel/arch/amd64/src/boot/multiboot.S
===================================================================
--- kernel/arch/amd64/src/boot/multiboot.S	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/amd64/src/boot/multiboot.S	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -76,4 +76,5 @@
 
 multiboot_image_start:
+	cli
 	cld
 	
@@ -81,6 +82,10 @@
 	movl $START_STACK, %esp
 	
-	/* Initialize Global Descriptor Table register */
+	/*
+	 * Initialize Global Descriptor Table and
+	 * Interrupt Descriptor Table registers
+	 */
 	lgdtl bootstrap_gdtr
+	lidtl bootstrap_idtr
 	
 	/* Kernel data + stack */
@@ -645,4 +650,9 @@
 .section K_DATA_START, "aw", @progbits
 
+.global bootstrap_idtr
+bootstrap_idtr:
+	.word 0
+	.long 0
+
 .global bootstrap_gdtr
 bootstrap_gdtr:
Index: kernel/arch/amd64/src/boot/multiboot2.S
===================================================================
--- kernel/arch/amd64/src/boot/multiboot2.S	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/amd64/src/boot/multiboot2.S	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -116,4 +116,5 @@
 
 multiboot2_image_start:
+	cli
 	cld
 	
@@ -121,6 +122,10 @@
 	movl $START_STACK, %esp
 	
-	/* Initialize Global Descriptor Table register */
+	/*
+	 * Initialize Global Descriptor Table and
+	 * Interrupt Descriptor Table registers
+	 */
 	lgdtl bootstrap_gdtr
+	lidtl bootstrap_idtr
 	
 	/* Kernel data + stack */
Index: kernel/arch/amd64/src/boot/vesa_ret.inc
===================================================================
--- kernel/arch/amd64/src/boot/vesa_ret.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/amd64/src/boot/vesa_ret.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -1,4 +1,5 @@
 .code32
 vesa_init_protected:
+	cli
 	cld
 	
Index: kernel/arch/amd64/src/mm/page.c
===================================================================
--- kernel/arch/amd64/src/mm/page.c	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/amd64/src/mm/page.c	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -57,5 +57,5 @@
 	uintptr_t cur;
 	unsigned int identity_flags =
-	    PAGE_CACHEABLE | PAGE_EXEC | PAGE_GLOBAL | PAGE_WRITE;
+	    PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ;
 		
 	page_mapping_operations = &pt_mapping_operations;
Index: kernel/arch/arm32/include/mm/page.h
===================================================================
--- kernel/arch/arm32/include/mm/page.h	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/arm32/include/mm/page.h	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -40,4 +40,5 @@
 #include <mm/mm.h>
 #include <arch/exception.h>
+#include <arch/barrier.h>
 #include <trace.h>
 
@@ -109,4 +110,12 @@
 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
 	set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
+
+/* Set PTE present bit accessors for each level. */
+#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
+	set_pt_level0_present((pte_t *) (ptl0), (size_t) (i))
+#define SET_PTL2_PRESENT_ARCH(ptl1, i)
+#define SET_PTL3_PRESENT_ARCH(ptl2, i)
+#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
+	set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
 
 /* Macros for querying the last-level PTE entries. */
@@ -267,4 +276,12 @@
 }
 
+NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
+{
+	pte_level0_t *p = &pt[i].l0;
+
+	p->should_be_zero = 0;
+	write_barrier();
+	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
+}
 
 /** Sets flags of level 1 page table entry.
@@ -283,11 +300,8 @@
 	pte_level1_t *p = &pt[i].l1;
 	
-	if (flags & PAGE_NOT_PRESENT) {
+	if (flags & PAGE_NOT_PRESENT)
 		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
-		p->access_permission_3 = 1;
-	} else {
+	else
 		p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-		p->access_permission_3 = p->access_permission_0;
-	}
 	
 	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
@@ -312,8 +326,13 @@
 }
 
-
+NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
+{
+	pte_level1_t *p = &pt[i].l1;
+
+	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+}
+	
 extern void page_arch_init(void);
 
-
 #endif /* __ASM__ */
 
Index: kernel/arch/ia32/include/mm/page.h
===================================================================
--- kernel/arch/ia32/include/mm/page.h	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/include/mm/page.h	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -115,4 +115,12 @@
 	set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
 
+/* Set PTE present bit accessors for each level. */
+#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
+	set_pt_present((pte_t *) (ptl0), (size_t) (i))
+#define SET_PTL2_PRESENT_ARCH(ptl1, i)
+#define SET_PTL3_PRESENT_ARCH(ptl2, i)
+#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
+	set_pt_present((pte_t *) (ptl3), (size_t) (i))
+
 /* Macros for querying the last level entries. */
 #define PTE_VALID_ARCH(p) \
@@ -194,4 +202,11 @@
 }
 
+NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+{
+	pte_t *p = &pt[i];
+
+	p->present = 1;
+}
+
 extern void page_arch_init(void);
 extern void page_fault(unsigned int, istate_t *);
Index: kernel/arch/ia32/src/boot/multiboot.S
===================================================================
--- kernel/arch/ia32/src/boot/multiboot.S	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/boot/multiboot.S	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -73,4 +73,5 @@
 
 multiboot_image_start:
+	cli
 	cld
 	
@@ -78,6 +79,10 @@
 	movl $START_STACK, %esp
 	
-	/* Initialize Global Descriptor Table register */
+	/*
+	 * Initialize Global Descriptor Table and
+	 * Interrupt Descriptor Table registers
+	 */
 	lgdtl bootstrap_gdtr
+	lidtl bootstrap_idtr
 	
 	/* Kernel data + stack */
@@ -701,4 +706,9 @@
 page_directory:
 	.space 4096, 0
+
+.global bootstrap_idtr
+bootstrap_idtr:
+	.word 0
+	.long 0
 
 .global bootstrap_gdtr
Index: kernel/arch/ia32/src/boot/multiboot2.S
===================================================================
--- kernel/arch/ia32/src/boot/multiboot2.S	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/boot/multiboot2.S	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -114,4 +114,5 @@
 
 multiboot2_image_start:
+	cli
 	cld
 	
@@ -119,6 +120,10 @@
 	movl $START_STACK, %esp
 	
-	/* Initialize Global Descriptor Table register */
+	/*
+	 * Initialize Global Descriptor Table and
+	 * Interrupt Descriptor Table registers
+	 */
 	lgdtl bootstrap_gdtr
+	lidtl bootstrap_idtr
 	
 	/* Kernel data + stack */
Index: kernel/arch/ia32/src/boot/vesa_prot.inc
===================================================================
--- kernel/arch/ia32/src/boot/vesa_prot.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/boot/vesa_prot.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -88,4 +88,11 @@
 		/* Returned back to protected mode */
 		
+		/*
+		 * Initialize Global Descriptor Table and
+		 * Interrupt Descriptor Table registers
+		 */
+		lgdtl bootstrap_gdtr
+		lidtl bootstrap_idtr
+		
 		movzx %ax, %ecx
 		mov %ecx, KA2PA(bfb_scanline)
Index: kernel/arch/ia32/src/boot/vesa_real.inc
===================================================================
--- kernel/arch/ia32/src/boot/vesa_real.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/boot/vesa_real.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -30,5 +30,10 @@
 .code32
 vesa_init:
+	lidtl vesa_idtr
 	jmp $GDT_SELECTOR(VESA_INIT_DES), $vesa_init_real - vesa_init
+
+vesa_idtr:
+	.word 0x3ff
+	.long 0
 
 .code16
Index: kernel/arch/ia32/src/boot/vesa_ret.inc
===================================================================
--- kernel/arch/ia32/src/boot/vesa_ret.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/boot/vesa_ret.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -1,4 +1,5 @@
 .code32
 vesa_init_protected:
+	cli
 	cld
 	
Index: kernel/arch/ia32/src/mm/page.c
===================================================================
--- kernel/arch/ia32/src/mm/page.c	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/mm/page.c	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -71,8 +71,5 @@
 	for (cur = 0; cur < min(config.identity_size, config.physmem_end);
 	    cur += FRAME_SIZE) {
-		flags = PAGE_CACHEABLE | PAGE_WRITE;
-		if ((PA2KA(cur) >= config.base) &&
-		    (PA2KA(cur) < config.base + config.kernel_size))
-			flags |= PAGE_GLOBAL;
+		flags = PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_WRITE | PAGE_READ;
 		page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
 	}
Index: kernel/arch/ia32/src/smp/apic.c
===================================================================
--- kernel/arch/ia32/src/smp/apic.c	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia32/src/smp/apic.c	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -259,9 +259,9 @@
 }
 
-static void ipi_wait_for_idle(void)
+/* Waits for the destination cpu to accept the previous ipi. */
+static void l_apic_wait_for_delivery(void)
 {
 	icr_t icr;
 	
-	/* Wait for the destination cpu to accept the previous ipi. */
 	do {
 		icr.lo = l_apic[ICRlo];
@@ -281,5 +281,5 @@
 
 	/* Wait for a destination cpu to accept our previous ipi. */
-	ipi_wait_for_idle();
+	l_apic_wait_for_delivery();
 	
 	icr.lo = l_apic[ICRlo];
@@ -298,11 +298,4 @@
 	l_apic[ICRlo] = icr.lo;
 	
-#ifdef CONFIG_DEBUG
-	icr.lo = l_apic[ICRlo];
-	if (icr.delivs == DELIVS_PENDING) {
-		printf("IPI is pending.\n");
-	}
-#endif
-	
 	return apic_poll_errors();
 }
@@ -320,5 +313,5 @@
 
 	/* Wait for a destination cpu to accept our previous ipi. */
-	ipi_wait_for_idle();
+	l_apic_wait_for_delivery();
 	
 	icr.lo = l_apic[ICRlo];
@@ -332,11 +325,4 @@
 	l_apic[ICRlo] = icr.lo;
 	
-	icr.lo = l_apic[ICRlo];
-	if (icr.delivs == DELIVS_PENDING) {
-#ifdef CONFIG_DEBUG
-		printf("IPI is pending.\n");
-#endif
-	}
-	
 	return apic_poll_errors();
 }
@@ -379,11 +365,7 @@
 		return 0;
 	
+	l_apic_wait_for_delivery();
+
 	icr.lo = l_apic[ICRlo];
-	if (icr.delivs == DELIVS_PENDING) {
-#ifdef CONFIG_DEBUG
-		printf("IPI is pending.\n");
-#endif
-	}
-	
 	icr.delmod = DELMOD_INIT;
 	icr.destmod = DESTMOD_PHYS;
@@ -518,14 +500,4 @@
 	dfr.model = MODEL_FLAT;
 	l_apic[DFR] = dfr.value;
-	
-	if (CPU->arch.id != l_apic_id()) {
-#ifdef CONFIG_DEBUG
-		printf("lapic error: LAPIC ID (%" PRIu8 ") and hw ID assigned by BSP"
-			" (%u) differ. Correcting to LAPIC ID.\n", l_apic_id(), 
-			CPU->arch.id);
-#endif
-		CPU->arch.id = l_apic_id();
-	}
-	
 }
 
Index: kernel/arch/ia64/Makefile.inc
===================================================================
--- kernel/arch/ia64/Makefile.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ia64/Makefile.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -30,5 +30,15 @@
 BFD_ARCH = ia64-elf64
 
-CMN1 = -mconstant-gp -fno-unwind-tables -mfixed-range=f32-f127
+#
+# FIXME:
+#
+# The -fno-selective-scheduling and -fno-selective-scheduling2 options
+# should be removed as soon as a bug in GCC concerning unchecked
+# speculative loads is fixed.
+#
+# See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53975 for reference.
+#
+
+CMN1 = -mconstant-gp -fno-unwind-tables -mfixed-range=f32-f127 -fno-selective-scheduling -fno-selective-scheduling2
 GCC_CFLAGS += $(CMN1)
 ICC_CFLAGS += $(CMN1)
Index: kernel/arch/mips32/Makefile.inc
===================================================================
--- kernel/arch/mips32/Makefile.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/mips32/Makefile.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -29,5 +29,5 @@
 BFD_ARCH = mips
 BFD = binary
-GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=32
+GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=32
 
 BITS = 32
@@ -48,5 +48,4 @@
 	BFD_NAME = elf32-tradlittlemips
 	ENDIANESS = LE
-	GCC_CFLAGS += -mhard-float
 endif
 
Index: kernel/arch/mips32/include/mm/page.h
===================================================================
--- kernel/arch/mips32/include/mm/page.h	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/mips32/include/mm/page.h	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -128,4 +128,12 @@
 	set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
 
+/* Set PTE present bit accessors for each level. */
+#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
+	set_pt_present((pte_t *) (ptl0), (size_t) (i))
+#define SET_PTL2_PRESENT_ARCH(ptl1, i)
+#define SET_PTL3_PRESENT_ARCH(ptl2, i)
+#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
+	set_pt_present((pte_t *) (ptl3), (size_t) (i))
+
 /* Last-level info macros. */
 #define PTE_VALID_ARCH(pte)			(*((uint32_t *) (pte)) != 0)
@@ -182,4 +190,12 @@
 }
 
+NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+{
+	pte_t *p = &pt[i];
+
+	p->p = 1;
+}
+	
+
 extern void page_arch_init(void);
 
Index: kernel/arch/mips64/Makefile.inc
===================================================================
--- kernel/arch/mips64/Makefile.inc	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/mips64/Makefile.inc	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -29,5 +29,5 @@
 BFD_ARCH = mips:4000
 BFD = binary
-GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=64
+GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=64
 AFLAGS = -64
 
@@ -40,5 +40,4 @@
 	BFD_NAME = elf64-tradlittlemips
 	ENDIANESS = LE
-	GCC_CFLAGS += -mhard-float
 endif
 
Index: kernel/arch/ppc32/include/mm/page.h
===================================================================
--- kernel/arch/ppc32/include/mm/page.h	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/ppc32/include/mm/page.h	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -128,4 +128,14 @@
 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
 	set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
+
+/* Set PTE present accessors for each level. */
+#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
+	set_pt_present((pte_t *) (ptl0), (size_t) (i))
+
+#define SET_PTL2_PRESENT_ARCH(ptl1, i)
+#define SET_PTL3_PRESENT_ARCH(ptl2, i)
+
+#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
+	set_pt_present((pte_t *) (ptl3), (size_t) (i))
 
 /* Macros for querying the last-level PTEs. */
@@ -175,4 +185,11 @@
 }
 
+NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+{
+	pte_t *entry = &pt[i];
+
+	entry->present = 1;
+}
+
 extern void page_arch_init(void);
 
Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision b17518ef2cd636e9ee2a4593e9e3f96130bd854b)
+++ kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision 7cfe5c035807f24eb685752e38192c922b60c893)
@@ -124,5 +124,5 @@
 			(void) interrupts_disable();
 		}
-	} while (done);
+	} while (!done);
 	
 	preemption_enable();