Index: kernel/arch/ia64/include/arch/context.h
===================================================================
--- kernel/arch/ia64/include/arch/context.h	(revision 0c27956d1f5181f0ff35db6c84835e3ecd3d27be)
+++ kernel/arch/ia64/include/arch/context.h	(revision 7cd7a8d678fba9c835468054b7578fabbbdf58d2)
@@ -57,4 +57,5 @@
 		(c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size / 2), REGISTER_STACK_ALIGNMENT); \
 		(c)->ar_pfs &= PFM_MASK; \
+		(c)->ar_fpsr = FPSR_TRAPS_ALL; \
 		(c)->sp = ((uintptr_t) stack) + ALIGN_UP((size / 2), STACK_ALIGNMENT) - SP_DELTA; \
 		(c)->r1 = (uintptr_t) &__gp; \
Index: kernel/arch/ia64/include/arch/context_struct.h
===================================================================
--- kernel/arch/ia64/include/arch/context_struct.h	(revision 0c27956d1f5181f0ff35db6c84835e3ecd3d27be)
+++ kernel/arch/ia64/include/arch/context_struct.h	(revision 7cd7a8d678fba9c835468054b7578fabbbdf58d2)
@@ -37,18 +37,19 @@
 #define CONTEXT_OFFSET_AR_RNAT         0x28
 #define CONTEXT_OFFSET_AR_LC           0x30
-#define CONTEXT_OFFSET_R1              0x38
-#define CONTEXT_OFFSET_R4              0x40
-#define CONTEXT_OFFSET_R5              0x48
-#define CONTEXT_OFFSET_R6              0x50
-#define CONTEXT_OFFSET_R7              0x58
-#define CONTEXT_OFFSET_SP              0x60
-#define CONTEXT_OFFSET_R13             0x68
-#define CONTEXT_OFFSET_PC              0x70
-#define CONTEXT_OFFSET_B1              0x78
-#define CONTEXT_OFFSET_B2              0x80
-#define CONTEXT_OFFSET_B3              0x88
-#define CONTEXT_OFFSET_B4              0x90
-#define CONTEXT_OFFSET_B5              0x98
-#define CONTEXT_OFFSET_PR              0xa0
+#define CONTEXT_OFFSET_AR_FPSR         0x38
+#define CONTEXT_OFFSET_R1              0x40
+#define CONTEXT_OFFSET_R4              0x48
+#define CONTEXT_OFFSET_R5              0x50
+#define CONTEXT_OFFSET_R6              0x58
+#define CONTEXT_OFFSET_R7              0x60
+#define CONTEXT_OFFSET_SP              0x68
+#define CONTEXT_OFFSET_R13             0x70
+#define CONTEXT_OFFSET_PC              0x78
+#define CONTEXT_OFFSET_B1              0x80
+#define CONTEXT_OFFSET_B2              0x88
+#define CONTEXT_OFFSET_B3              0x90
+#define CONTEXT_OFFSET_B4              0x98
+#define CONTEXT_OFFSET_B5              0xa0
+#define CONTEXT_OFFSET_PR              0xa8
 #define CONTEXT_OFFSET_F2              0xb0
 #define CONTEXT_OFFSET_F3              0xc0
@@ -89,4 +90,5 @@
 	uint64_t ar_rnat;
 	uint64_t ar_lc;
+	uint64_t ar_fpsr;
 
 	// General registers.
@@ -111,4 +113,6 @@
 	// Predicate registers.
 	uint64_t pr;
+
+	// Floating-point registers.
 	uint128_t f2;
 	uint128_t f3;
Index: kernel/arch/ia64/include/arch/register.h
===================================================================
--- kernel/arch/ia64/include/arch/register.h	(revision 0c27956d1f5181f0ff35db6c84835e3ecd3d27be)
+++ kernel/arch/ia64/include/arch/register.h	(revision 7cd7a8d678fba9c835468054b7578fabbbdf58d2)
@@ -68,4 +68,14 @@
 #define RSC_MODE_MASK   3
 #define RSC_PL_MASK     12
+
+#define FPSR_TRAPS_VD  (1 << 0)
+#define FPSR_TRAPS_DD  (1 << 1)
+#define FPSR_TRAPS_ZD  (1 << 2)
+#define FPSR_TRAPS_OD  (1 << 3)
+#define FPSR_TRAPS_UD  (1 << 4)
+#define FPSR_TRAPS_ID  (1 << 5)
+
+#define FPSR_TRAPS_ALL (FPSR_TRAPS_VD | FPSR_TRAPS_DD | FPSR_TRAPS_ZD | \
+    FPSR_TRAPS_OD | FPSR_TRAPS_UD | FPSR_TRAPS_ID)
 
 /** Application registers. */
Index: kernel/arch/ia64/src/context.S
===================================================================
--- kernel/arch/ia64/src/context.S	(revision 0c27956d1f5181f0ff35db6c84835e3ecd3d27be)
+++ kernel/arch/ia64/src/context.S	(revision 7cd7a8d678fba9c835468054b7578fabbbdf58d2)
@@ -33,5 +33,5 @@
 
 FUNCTION_BEGIN(context_save_arch)
-	alloc loc0 = ar.pfs, 1, 49, 0, 0
+	alloc loc0 = ar.pfs, 1, 50, 0, 0
 	mov loc1 = ar.unat ;;
 	mov loc3 = ar.rsc
@@ -57,4 +57,5 @@
 
 	mov loc6 = ar.lc
+	mov loc7 = ar.fpsr
 
 	add loc8 = CONTEXT_OFFSET_AR_PFS, in0
@@ -65,131 +66,5 @@
 	add loc13 = CONTEXT_OFFSET_AR_RNAT, in0
 	add loc14 = CONTEXT_OFFSET_AR_LC, in0
-
-	add loc15 = CONTEXT_OFFSET_R1, in0
-	add loc16 = CONTEXT_OFFSET_R4, in0
-	add loc17 = CONTEXT_OFFSET_R5, in0
-	add loc18 = CONTEXT_OFFSET_R6, in0
-	add loc19 = CONTEXT_OFFSET_R7, in0
-	add loc20 = CONTEXT_OFFSET_SP, in0
-	add loc21 = CONTEXT_OFFSET_R13, in0
-
-	add loc22 = CONTEXT_OFFSET_PC, in0
-	add loc23 = CONTEXT_OFFSET_B1, in0
-	add loc24 = CONTEXT_OFFSET_B2, in0
-	add loc25 = CONTEXT_OFFSET_B3, in0
-	add loc26 = CONTEXT_OFFSET_B4, in0
-	add loc27 = CONTEXT_OFFSET_B5, in0
-
-	add loc28 = CONTEXT_OFFSET_PR, in0
-
-	add loc29 = CONTEXT_OFFSET_F2, in0
-	add loc30 = CONTEXT_OFFSET_F3, in0
-	add loc31 = CONTEXT_OFFSET_F4, in0
-	add loc32 = CONTEXT_OFFSET_F5, in0
-
-	add loc33 = CONTEXT_OFFSET_F16, in0
-	add loc34 = CONTEXT_OFFSET_F17, in0
-	add loc35 = CONTEXT_OFFSET_F18, in0
-	add loc36 = CONTEXT_OFFSET_F19, in0
-	add loc37 = CONTEXT_OFFSET_F20, in0
-	add loc38 = CONTEXT_OFFSET_F21, in0
-	add loc39 = CONTEXT_OFFSET_F22, in0
-	add loc40 = CONTEXT_OFFSET_F23, in0
-	add loc41 = CONTEXT_OFFSET_F24, in0
-	add loc42 = CONTEXT_OFFSET_F25, in0
-	add loc43 = CONTEXT_OFFSET_F26, in0
-	add loc44 = CONTEXT_OFFSET_F27, in0
-	add loc45 = CONTEXT_OFFSET_F28, in0
-	add loc46 = CONTEXT_OFFSET_F29, in0
-	add loc47 = CONTEXT_OFFSET_F30, in0
-	add loc48 = CONTEXT_OFFSET_F31, in0 ;;
-
-	/*
-	 * Save general registers including NaT bits
-	 */
-	st8.spill [loc15] = r1 ;;
-	st8.spill [loc16] = r4 ;;
-	st8.spill [loc17] = r5 ;;
-	st8.spill [loc18] = r6 ;;
-	st8.spill [loc19] = r7 ;;
-	st8.spill [loc20] = r12	;;	/* save sp */
-	st8.spill [loc21] = r13 ;;
-
-	mov loc2 = ar.unat
-
-	/*
-	 * Save application registers
-	 */
-	st8 [loc8] = loc0	/* save ar.pfs */
-	st8 [loc9] = loc1 ;;	/* save ar.unat (caller) */
-	st8 [loc10] = loc2	/* save ar.unat (callee) */
-	st8 [loc11] = loc3	/* save ar.rsc */
-	st8 [loc12] = loc4	/* save ar.bsp */
-	st8 [loc13] = loc5	/* save ar.rnat */
-	st8 [loc14] = loc6 ;;	/* save ar.lc */
-
-	/*
-	 * Save branch registers
-	 */
-	mov loc2 = b0
-	mov loc3 = b1
-	mov loc4 = b2
-	mov loc5 = b3
-	mov loc6 = b4
-	mov loc7 = b5 ;;
-	st8 [loc22] = loc2	/* save pc */
-	st8 [loc23] = loc3
-	st8 [loc24] = loc4
-	st8 [loc25] = loc5
-	st8 [loc26] = loc6
-	st8 [loc27] = loc7 ;;
-
-	/*
-	 * Save predicate registers
-	 */
-	mov loc2 = pr ;;
-	st8 [loc28] = loc2
-
-	/*
-	 * Save floating-point registers.
-	 */
-	stf.spill [loc29] = f2
-	stf.spill [loc30] = f3
-	stf.spill [loc31] = f4
-	stf.spill [loc32] = f5
-
-	stf.spill [loc33] = f16
-	stf.spill [loc34] = f17
-	stf.spill [loc35] = f18
-	stf.spill [loc36] = f19
-	stf.spill [loc37] = f20
-	stf.spill [loc38] = f21
-	stf.spill [loc39] = f22
-	stf.spill [loc40] = f23
-	stf.spill [loc41] = f24
-	stf.spill [loc42] = f25
-	stf.spill [loc43] = f26
-	stf.spill [loc44] = f27
-	stf.spill [loc45] = f28
-	stf.spill [loc46] = f29
-	stf.spill [loc47] = f30
-	stf.spill [loc48] = f31
-
-	mov ar.unat = loc1
-
-	add r8 = r0, r0, 1 	/* context_save returns 1 */
-	br.ret.sptk.many b0
-FUNCTION_END(context_save_arch)
-
-FUNCTION_BEGIN(context_restore_arch)
-	alloc loc0 = ar.pfs, 1, 50, 0, 0	;;
-
-	add loc9 = CONTEXT_OFFSET_AR_PFS, in0
-	add loc10 = CONTEXT_OFFSET_AR_UNAT_CALLER, in0
-	add loc11 = CONTEXT_OFFSET_AR_UNAT_CALLEE, in0
-	add loc12 = CONTEXT_OFFSET_AR_RSC, in0
-	add loc13 = CONTEXT_OFFSET_BSP, in0
-	add loc14 = CONTEXT_OFFSET_AR_RNAT, in0
-	add loc15 = CONTEXT_OFFSET_AR_LC, in0
+	add loc15 = CONTEXT_OFFSET_AR_FPSR, in0
 
 	add loc16 = CONTEXT_OFFSET_R1, in0
@@ -232,4 +107,133 @@
 	add loc49 = CONTEXT_OFFSET_F31, in0 ;;
 
+	/*
+	 * Save general registers including NaT bits
+	 */
+	st8.spill [loc16] = r1 ;;
+	st8.spill [loc17] = r4 ;;
+	st8.spill [loc18] = r5 ;;
+	st8.spill [loc19] = r6 ;;
+	st8.spill [loc20] = r7 ;;
+	st8.spill [loc21] = r12	;;	/* save sp */
+	st8.spill [loc22] = r13 ;;
+
+	mov loc2 = ar.unat
+
+	/*
+	 * Save application registers
+	 */
+	st8 [loc8] = loc0	/* save ar.pfs */
+	st8 [loc9] = loc1 ;;	/* save ar.unat (caller) */
+	st8 [loc10] = loc2	/* save ar.unat (callee) */
+	st8 [loc11] = loc3	/* save ar.rsc */
+	st8 [loc12] = loc4	/* save ar.bsp */
+	st8 [loc13] = loc5	/* save ar.rnat */
+	st8 [loc14] = loc6	/* save ar.lc */
+	st8 [loc15] = loc7 ;;	/* save ar.fpsr */
+
+	/*
+	 * Save branch registers
+	 */
+	mov loc2 = b0
+	mov loc3 = b1
+	mov loc4 = b2
+	mov loc5 = b3
+	mov loc6 = b4
+	mov loc7 = b5 ;;
+	st8 [loc23] = loc2	/* save pc */
+	st8 [loc24] = loc3
+	st8 [loc25] = loc4
+	st8 [loc26] = loc5
+	st8 [loc27] = loc6
+	st8 [loc28] = loc7 ;;
+
+	/*
+	 * Save predicate registers
+	 */
+	mov loc2 = pr ;;
+	st8 [loc29] = loc2
+
+	/*
+	 * Save floating-point registers.
+	 */
+	stf.spill [loc30] = f2
+	stf.spill [loc31] = f3
+	stf.spill [loc32] = f4
+	stf.spill [loc33] = f5
+
+	stf.spill [loc34] = f16
+	stf.spill [loc35] = f17
+	stf.spill [loc36] = f18
+	stf.spill [loc37] = f19
+	stf.spill [loc38] = f20
+	stf.spill [loc39] = f21
+	stf.spill [loc40] = f22
+	stf.spill [loc41] = f23
+	stf.spill [loc42] = f24
+	stf.spill [loc43] = f25
+	stf.spill [loc44] = f26
+	stf.spill [loc45] = f27
+	stf.spill [loc46] = f28
+	stf.spill [loc47] = f29
+	stf.spill [loc48] = f30
+	stf.spill [loc49] = f31
+
+	mov ar.unat = loc1
+
+	add r8 = r0, r0, 1 	/* context_save returns 1 */
+	br.ret.sptk.many b0
+FUNCTION_END(context_save_arch)
+
+FUNCTION_BEGIN(context_restore_arch)
+	alloc loc0 = ar.pfs, 1, 51, 0, 0 ;;
+
+	add loc9 = CONTEXT_OFFSET_AR_PFS, in0
+	add loc10 = CONTEXT_OFFSET_AR_UNAT_CALLER, in0
+	add loc11 = CONTEXT_OFFSET_AR_UNAT_CALLEE, in0
+	add loc12 = CONTEXT_OFFSET_AR_RSC, in0
+	add loc13 = CONTEXT_OFFSET_BSP, in0
+	add loc14 = CONTEXT_OFFSET_AR_RNAT, in0
+	add loc15 = CONTEXT_OFFSET_AR_LC, in0
+	add loc16 = CONTEXT_OFFSET_AR_FPSR, in0
+
+	add loc17 = CONTEXT_OFFSET_R1, in0
+	add loc18 = CONTEXT_OFFSET_R4, in0
+	add loc19 = CONTEXT_OFFSET_R5, in0
+	add loc20 = CONTEXT_OFFSET_R6, in0
+	add loc21 = CONTEXT_OFFSET_R7, in0
+	add loc22 = CONTEXT_OFFSET_SP, in0
+	add loc23 = CONTEXT_OFFSET_R13, in0
+
+	add loc24 = CONTEXT_OFFSET_PC, in0
+	add loc25 = CONTEXT_OFFSET_B1, in0
+	add loc26 = CONTEXT_OFFSET_B2, in0
+	add loc27 = CONTEXT_OFFSET_B3, in0
+	add loc28 = CONTEXT_OFFSET_B4, in0
+	add loc29 = CONTEXT_OFFSET_B5, in0
+
+	add loc30 = CONTEXT_OFFSET_PR, in0
+
+	add loc31 = CONTEXT_OFFSET_F2, in0
+	add loc32 = CONTEXT_OFFSET_F3, in0
+	add loc33 = CONTEXT_OFFSET_F4, in0
+	add loc34 = CONTEXT_OFFSET_F5, in0
+
+	add loc35 = CONTEXT_OFFSET_F16, in0
+	add loc36 = CONTEXT_OFFSET_F17, in0
+	add loc37 = CONTEXT_OFFSET_F18, in0
+	add loc38 = CONTEXT_OFFSET_F19, in0
+	add loc39 = CONTEXT_OFFSET_F20, in0
+	add loc40 = CONTEXT_OFFSET_F21, in0
+	add loc41 = CONTEXT_OFFSET_F22, in0
+	add loc42 = CONTEXT_OFFSET_F23, in0
+	add loc43 = CONTEXT_OFFSET_F24, in0
+	add loc44 = CONTEXT_OFFSET_F25, in0
+	add loc45 = CONTEXT_OFFSET_F26, in0
+	add loc46 = CONTEXT_OFFSET_F27, in0
+	add loc47 = CONTEXT_OFFSET_F28, in0
+	add loc48 = CONTEXT_OFFSET_F29, in0
+	add loc49 = CONTEXT_OFFSET_F30, in0
+	add loc50 = CONTEXT_OFFSET_F31, in0 ;;
+
 	ld8 loc0 = [loc9]	/* load ar.pfs */
 	ld8 loc1 = [loc10]	/* load ar.unat (caller) */
@@ -239,4 +243,5 @@
 	ld8 loc5 = [loc14]	/* load ar.rnat */
 	ld8 loc6 = [loc15]	/* load ar.lc */
+	ld8 loc7 = [loc16]	/* load ar.fpsr */
 
 	.auto
@@ -269,4 +274,5 @@
 	mov ar.pfs = loc0
 	mov ar.rsc = loc3
+	mov ar.fpsr = loc7
 
 	.explicit
@@ -278,21 +284,21 @@
 	 * Restore general registers including NaT bits
 	 */
-	ld8.fill r1 = [loc16] ;;
-	ld8.fill r4 = [loc17] ;;
-	ld8.fill r5 = [loc18] ;;
-	ld8.fill r6 = [loc19] ;;
-	ld8.fill r7 = [loc20] ;;
-	ld8.fill r12 = [loc21] ;;	/* restore sp */
-	ld8.fill r13 = [loc22] ;;
+	ld8.fill r1 = [loc17] ;;
+	ld8.fill r4 = [loc18] ;;
+	ld8.fill r5 = [loc19] ;;
+	ld8.fill r6 = [loc20] ;;
+	ld8.fill r7 = [loc21] ;;
+	ld8.fill r12 = [loc22] ;;	/* restore sp */
+	ld8.fill r13 = [loc23] ;;
 
 	/*
 	 * Restore branch registers
 	 */
-	ld8 loc2 = [loc23]		/* restore pc */
-	ld8 loc3 = [loc24]
-	ld8 loc4 = [loc25]
-	ld8 loc5 = [loc26]
-	ld8 loc6 = [loc27]
-	ld8 loc7 = [loc28] ;;
+	ld8 loc2 = [loc24]		/* restore pc */
+	ld8 loc3 = [loc25]
+	ld8 loc4 = [loc26]
+	ld8 loc5 = [loc27]
+	ld8 loc6 = [loc28]
+	ld8 loc7 = [loc29] ;;
 	mov b0 = loc2
 	mov b1 = loc3
@@ -305,5 +311,5 @@
 	 * Restore predicate registers
 	 */
-	ld8 loc2 = [loc29] ;;
+	ld8 loc2 = [loc30] ;;
 	mov pr = loc2, ~0
 
@@ -311,25 +317,25 @@
 	 * Restore floating-point registers.
 	 */
-	ldf.fill f2 = [loc30]
-	ldf.fill f3 = [loc31]
-	ldf.fill f4 = [loc32]
-	ldf.fill f5 = [loc33]
-
-	ldf.fill f16 = [loc34]
-	ldf.fill f17 = [loc35]
-	ldf.fill f18 = [loc36]
-	ldf.fill f19 = [loc37]
-	ldf.fill f20 = [loc38]
-	ldf.fill f21 = [loc39]
-	ldf.fill f22 = [loc40]
-	ldf.fill f23 = [loc41]
-	ldf.fill f24 = [loc42]
-	ldf.fill f25 = [loc43]
-	ldf.fill f26 = [loc44]
-	ldf.fill f27 = [loc45]
-	ldf.fill f28 = [loc46]
-	ldf.fill f29 = [loc47]
-	ldf.fill f30 = [loc48]
-	ldf.fill f31 = [loc49]
+	ldf.fill f2 = [loc31]
+	ldf.fill f3 = [loc32]
+	ldf.fill f4 = [loc33]
+	ldf.fill f5 = [loc34]
+
+	ldf.fill f16 = [loc35]
+	ldf.fill f17 = [loc36]
+	ldf.fill f18 = [loc37]
+	ldf.fill f19 = [loc38]
+	ldf.fill f20 = [loc39]
+	ldf.fill f21 = [loc40]
+	ldf.fill f22 = [loc41]
+	ldf.fill f23 = [loc42]
+	ldf.fill f24 = [loc43]
+	ldf.fill f25 = [loc44]
+	ldf.fill f26 = [loc45]
+	ldf.fill f27 = [loc46]
+	ldf.fill f28 = [loc47]
+	ldf.fill f29 = [loc48]
+	ldf.fill f30 = [loc49]
+	ldf.fill f31 = [loc50]
 
 	mov ar.unat = loc1
Index: kernel/arch/ia64/src/fpu_context.c
===================================================================
--- kernel/arch/ia64/src/fpu_context.c	(revision 0c27956d1f5181f0ff35db6c84835e3ecd3d27be)
+++ kernel/arch/ia64/src/fpu_context.c	(revision 7cd7a8d678fba9c835468054b7578fabbbdf58d2)
@@ -462,6 +462,4 @@
 void fpu_enable(void)
 {
-	uint64_t a = 0;
-
 	asm volatile (
 	    "rsm %0 ;;"
@@ -471,18 +469,8 @@
 	    : "i" (PSR_DFH_MASK)
 	);
-
-	asm volatile (
-	    "mov %0 = ar.fpsr ;;\n"
-	    "or %0 = %0,%1 ;;\n"
-	    "mov ar.fpsr = %0 ;;\n"
-	    : "+r" (a)
-	    : "r" (0x38)
-	);
 }
 
 void fpu_disable(void)
 {
-	uint64_t a = 0;
-
 	asm volatile (
 	    "ssm %0 ;;\n"
@@ -492,4 +480,9 @@
 	    : "i" (PSR_DFH_MASK)
 	);
+}
+
+void fpu_init(void)
+{
+	uint64_t a = 0;
 
 	asm volatile (
@@ -498,18 +491,5 @@
 	    "mov ar.fpsr = %0 ;;\n"
 	    : "+r" (a)
-	    : "r" (0x38)
-	);
-}
-
-void fpu_init(void)
-{
-	uint64_t a = 0;
-
-	asm volatile (
-	    "mov %0 = ar.fpsr ;;\n"
-	    "or %0 = %0,%1 ;;\n"
-	    "mov ar.fpsr = %0 ;;\n"
-	    : "+r" (a)
-	    : "r" (0x38)
+	    : "r" (FPSR_TRAPS_ALL)
 	);