Changeset 7cd7a8d in mainline
- Timestamp:
- 2018-08-02T20:38:05Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9b7adc38
- Parents:
- 0c27956
- git-author:
- Jakub Jermar <jakub@…> (2018-08-01 22:48:10)
- git-committer:
- Jakub Jermar <jakub@…> (2018-08-02 20:38:05)
- Location:
- kernel/arch/ia64
- Files:
-
- 5 edited
-
include/arch/context.h (modified) (1 diff)
-
include/arch/context_struct.h (modified) (3 diffs)
-
include/arch/register.h (modified) (1 diff)
-
src/context.S (modified) (9 diffs)
-
src/fpu_context.c (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia64/include/arch/context.h
r0c27956 r7cd7a8d 57 57 (c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size / 2), REGISTER_STACK_ALIGNMENT); \ 58 58 (c)->ar_pfs &= PFM_MASK; \ 59 (c)->ar_fpsr = FPSR_TRAPS_ALL; \ 59 60 (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size / 2), STACK_ALIGNMENT) - SP_DELTA; \ 60 61 (c)->r1 = (uintptr_t) &__gp; \ -
kernel/arch/ia64/include/arch/context_struct.h
r0c27956 r7cd7a8d 37 37 #define CONTEXT_OFFSET_AR_RNAT 0x28 38 38 #define CONTEXT_OFFSET_AR_LC 0x30 39 #define CONTEXT_OFFSET_R1 0x38 40 #define CONTEXT_OFFSET_R4 0x40 41 #define CONTEXT_OFFSET_R5 0x48 42 #define CONTEXT_OFFSET_R6 0x50 43 #define CONTEXT_OFFSET_R7 0x58 44 #define CONTEXT_OFFSET_SP 0x60 45 #define CONTEXT_OFFSET_R13 0x68 46 #define CONTEXT_OFFSET_PC 0x70 47 #define CONTEXT_OFFSET_B1 0x78 48 #define CONTEXT_OFFSET_B2 0x80 49 #define CONTEXT_OFFSET_B3 0x88 50 #define CONTEXT_OFFSET_B4 0x90 51 #define CONTEXT_OFFSET_B5 0x98 52 #define CONTEXT_OFFSET_PR 0xa0 39 #define CONTEXT_OFFSET_AR_FPSR 0x38 40 #define CONTEXT_OFFSET_R1 0x40 41 #define CONTEXT_OFFSET_R4 0x48 42 #define CONTEXT_OFFSET_R5 0x50 43 #define CONTEXT_OFFSET_R6 0x58 44 #define CONTEXT_OFFSET_R7 0x60 45 #define CONTEXT_OFFSET_SP 0x68 46 #define CONTEXT_OFFSET_R13 0x70 47 #define CONTEXT_OFFSET_PC 0x78 48 #define CONTEXT_OFFSET_B1 0x80 49 #define CONTEXT_OFFSET_B2 0x88 50 #define CONTEXT_OFFSET_B3 0x90 51 #define CONTEXT_OFFSET_B4 0x98 52 #define CONTEXT_OFFSET_B5 0xa0 53 #define CONTEXT_OFFSET_PR 0xa8 53 54 #define CONTEXT_OFFSET_F2 0xb0 54 55 #define CONTEXT_OFFSET_F3 0xc0 … … 89 90 uint64_t ar_rnat; 90 91 uint64_t ar_lc; 92 uint64_t ar_fpsr; 91 93 92 94 // General registers. … … 111 113 // Predicate registers. 112 114 uint64_t pr; 115 116 // Floating-point registers. 113 117 uint128_t f2; 114 118 uint128_t f3; -
kernel/arch/ia64/include/arch/register.h
r0c27956 r7cd7a8d 68 68 #define RSC_MODE_MASK 3 69 69 #define RSC_PL_MASK 12 70 71 #define FPSR_TRAPS_VD (1 << 0) 72 #define FPSR_TRAPS_DD (1 << 1) 73 #define FPSR_TRAPS_ZD (1 << 2) 74 #define FPSR_TRAPS_OD (1 << 3) 75 #define FPSR_TRAPS_UD (1 << 4) 76 #define FPSR_TRAPS_ID (1 << 5) 77 78 #define FPSR_TRAPS_ALL (FPSR_TRAPS_VD | FPSR_TRAPS_DD | FPSR_TRAPS_ZD | \ 79 FPSR_TRAPS_OD | FPSR_TRAPS_UD | FPSR_TRAPS_ID) 70 80 71 81 /** Application registers. */ -
kernel/arch/ia64/src/context.S
r0c27956 r7cd7a8d 33 33 34 34 FUNCTION_BEGIN(context_save_arch) 35 alloc loc0 = ar.pfs, 1, 49, 0, 035 alloc loc0 = ar.pfs, 1, 50, 0, 0 36 36 mov loc1 = ar.unat ;; 37 37 mov loc3 = ar.rsc … … 57 57 58 58 mov loc6 = ar.lc 59 mov loc7 = ar.fpsr 59 60 60 61 add loc8 = CONTEXT_OFFSET_AR_PFS, in0 … … 65 66 add loc13 = CONTEXT_OFFSET_AR_RNAT, in0 66 67 add loc14 = CONTEXT_OFFSET_AR_LC, in0 67 68 add loc15 = CONTEXT_OFFSET_R1, in0 69 add loc16 = CONTEXT_OFFSET_R4, in0 70 add loc17 = CONTEXT_OFFSET_R5, in0 71 add loc18 = CONTEXT_OFFSET_R6, in0 72 add loc19 = CONTEXT_OFFSET_R7, in0 73 add loc20 = CONTEXT_OFFSET_SP, in0 74 add loc21 = CONTEXT_OFFSET_R13, in0 75 76 add loc22 = CONTEXT_OFFSET_PC, in0 77 add loc23 = CONTEXT_OFFSET_B1, in0 78 add loc24 = CONTEXT_OFFSET_B2, in0 79 add loc25 = CONTEXT_OFFSET_B3, in0 80 add loc26 = CONTEXT_OFFSET_B4, in0 81 add loc27 = CONTEXT_OFFSET_B5, in0 82 83 add loc28 = CONTEXT_OFFSET_PR, in0 84 85 add loc29 = CONTEXT_OFFSET_F2, in0 86 add loc30 = CONTEXT_OFFSET_F3, in0 87 add loc31 = CONTEXT_OFFSET_F4, in0 88 add loc32 = CONTEXT_OFFSET_F5, in0 89 90 add loc33 = CONTEXT_OFFSET_F16, in0 91 add loc34 = CONTEXT_OFFSET_F17, in0 92 add loc35 = CONTEXT_OFFSET_F18, in0 93 add loc36 = CONTEXT_OFFSET_F19, in0 94 add loc37 = CONTEXT_OFFSET_F20, in0 95 add loc38 = CONTEXT_OFFSET_F21, in0 96 add loc39 = CONTEXT_OFFSET_F22, in0 97 add loc40 = CONTEXT_OFFSET_F23, in0 98 add loc41 = CONTEXT_OFFSET_F24, in0 99 add loc42 = CONTEXT_OFFSET_F25, in0 100 add loc43 = CONTEXT_OFFSET_F26, in0 101 add loc44 = CONTEXT_OFFSET_F27, in0 102 add loc45 = CONTEXT_OFFSET_F28, in0 103 add loc46 = CONTEXT_OFFSET_F29, in0 104 add loc47 = CONTEXT_OFFSET_F30, in0 105 add loc48 = CONTEXT_OFFSET_F31, in0 ;; 106 107 /* 108 * Save general registers including NaT bits 109 */ 110 st8.spill [loc15] = r1 ;; 111 st8.spill [loc16] = r4 ;; 112 st8.spill [loc17] = r5 ;; 113 st8.spill [loc18] = r6 ;; 114 st8.spill [loc19] = r7 ;; 115 st8.spill [loc20] = r12 ;; /* save sp */ 116 st8.spill [loc21] = r13 ;; 117 118 mov loc2 = ar.unat 119 120 /* 121 * Save application registers 122 */ 123 st8 [loc8] = loc0 /* save ar.pfs */ 124 st8 [loc9] = loc1 ;; /* save ar.unat (caller) */ 125 st8 [loc10] = loc2 /* save ar.unat (callee) */ 126 st8 [loc11] = loc3 /* save ar.rsc */ 127 st8 [loc12] = loc4 /* save ar.bsp */ 128 st8 [loc13] = loc5 /* save ar.rnat */ 129 st8 [loc14] = loc6 ;; /* save ar.lc */ 130 131 /* 132 * Save branch registers 133 */ 134 mov loc2 = b0 135 mov loc3 = b1 136 mov loc4 = b2 137 mov loc5 = b3 138 mov loc6 = b4 139 mov loc7 = b5 ;; 140 st8 [loc22] = loc2 /* save pc */ 141 st8 [loc23] = loc3 142 st8 [loc24] = loc4 143 st8 [loc25] = loc5 144 st8 [loc26] = loc6 145 st8 [loc27] = loc7 ;; 146 147 /* 148 * Save predicate registers 149 */ 150 mov loc2 = pr ;; 151 st8 [loc28] = loc2 152 153 /* 154 * Save floating-point registers. 155 */ 156 stf.spill [loc29] = f2 157 stf.spill [loc30] = f3 158 stf.spill [loc31] = f4 159 stf.spill [loc32] = f5 160 161 stf.spill [loc33] = f16 162 stf.spill [loc34] = f17 163 stf.spill [loc35] = f18 164 stf.spill [loc36] = f19 165 stf.spill [loc37] = f20 166 stf.spill [loc38] = f21 167 stf.spill [loc39] = f22 168 stf.spill [loc40] = f23 169 stf.spill [loc41] = f24 170 stf.spill [loc42] = f25 171 stf.spill [loc43] = f26 172 stf.spill [loc44] = f27 173 stf.spill [loc45] = f28 174 stf.spill [loc46] = f29 175 stf.spill [loc47] = f30 176 stf.spill [loc48] = f31 177 178 mov ar.unat = loc1 179 180 add r8 = r0, r0, 1 /* context_save returns 1 */ 181 br.ret.sptk.many b0 182 FUNCTION_END(context_save_arch) 183 184 FUNCTION_BEGIN(context_restore_arch) 185 alloc loc0 = ar.pfs, 1, 50, 0, 0 ;; 186 187 add loc9 = CONTEXT_OFFSET_AR_PFS, in0 188 add loc10 = CONTEXT_OFFSET_AR_UNAT_CALLER, in0 189 add loc11 = CONTEXT_OFFSET_AR_UNAT_CALLEE, in0 190 add loc12 = CONTEXT_OFFSET_AR_RSC, in0 191 add loc13 = CONTEXT_OFFSET_BSP, in0 192 add loc14 = CONTEXT_OFFSET_AR_RNAT, in0 193 add loc15 = CONTEXT_OFFSET_AR_LC, in0 68 add loc15 = CONTEXT_OFFSET_AR_FPSR, in0 194 69 195 70 add loc16 = CONTEXT_OFFSET_R1, in0 … … 232 107 add loc49 = CONTEXT_OFFSET_F31, in0 ;; 233 108 109 /* 110 * Save general registers including NaT bits 111 */ 112 st8.spill [loc16] = r1 ;; 113 st8.spill [loc17] = r4 ;; 114 st8.spill [loc18] = r5 ;; 115 st8.spill [loc19] = r6 ;; 116 st8.spill [loc20] = r7 ;; 117 st8.spill [loc21] = r12 ;; /* save sp */ 118 st8.spill [loc22] = r13 ;; 119 120 mov loc2 = ar.unat 121 122 /* 123 * Save application registers 124 */ 125 st8 [loc8] = loc0 /* save ar.pfs */ 126 st8 [loc9] = loc1 ;; /* save ar.unat (caller) */ 127 st8 [loc10] = loc2 /* save ar.unat (callee) */ 128 st8 [loc11] = loc3 /* save ar.rsc */ 129 st8 [loc12] = loc4 /* save ar.bsp */ 130 st8 [loc13] = loc5 /* save ar.rnat */ 131 st8 [loc14] = loc6 /* save ar.lc */ 132 st8 [loc15] = loc7 ;; /* save ar.fpsr */ 133 134 /* 135 * Save branch registers 136 */ 137 mov loc2 = b0 138 mov loc3 = b1 139 mov loc4 = b2 140 mov loc5 = b3 141 mov loc6 = b4 142 mov loc7 = b5 ;; 143 st8 [loc23] = loc2 /* save pc */ 144 st8 [loc24] = loc3 145 st8 [loc25] = loc4 146 st8 [loc26] = loc5 147 st8 [loc27] = loc6 148 st8 [loc28] = loc7 ;; 149 150 /* 151 * Save predicate registers 152 */ 153 mov loc2 = pr ;; 154 st8 [loc29] = loc2 155 156 /* 157 * Save floating-point registers. 158 */ 159 stf.spill [loc30] = f2 160 stf.spill [loc31] = f3 161 stf.spill [loc32] = f4 162 stf.spill [loc33] = f5 163 164 stf.spill [loc34] = f16 165 stf.spill [loc35] = f17 166 stf.spill [loc36] = f18 167 stf.spill [loc37] = f19 168 stf.spill [loc38] = f20 169 stf.spill [loc39] = f21 170 stf.spill [loc40] = f22 171 stf.spill [loc41] = f23 172 stf.spill [loc42] = f24 173 stf.spill [loc43] = f25 174 stf.spill [loc44] = f26 175 stf.spill [loc45] = f27 176 stf.spill [loc46] = f28 177 stf.spill [loc47] = f29 178 stf.spill [loc48] = f30 179 stf.spill [loc49] = f31 180 181 mov ar.unat = loc1 182 183 add r8 = r0, r0, 1 /* context_save returns 1 */ 184 br.ret.sptk.many b0 185 FUNCTION_END(context_save_arch) 186 187 FUNCTION_BEGIN(context_restore_arch) 188 alloc loc0 = ar.pfs, 1, 51, 0, 0 ;; 189 190 add loc9 = CONTEXT_OFFSET_AR_PFS, in0 191 add loc10 = CONTEXT_OFFSET_AR_UNAT_CALLER, in0 192 add loc11 = CONTEXT_OFFSET_AR_UNAT_CALLEE, in0 193 add loc12 = CONTEXT_OFFSET_AR_RSC, in0 194 add loc13 = CONTEXT_OFFSET_BSP, in0 195 add loc14 = CONTEXT_OFFSET_AR_RNAT, in0 196 add loc15 = CONTEXT_OFFSET_AR_LC, in0 197 add loc16 = CONTEXT_OFFSET_AR_FPSR, in0 198 199 add loc17 = CONTEXT_OFFSET_R1, in0 200 add loc18 = CONTEXT_OFFSET_R4, in0 201 add loc19 = CONTEXT_OFFSET_R5, in0 202 add loc20 = CONTEXT_OFFSET_R6, in0 203 add loc21 = CONTEXT_OFFSET_R7, in0 204 add loc22 = CONTEXT_OFFSET_SP, in0 205 add loc23 = CONTEXT_OFFSET_R13, in0 206 207 add loc24 = CONTEXT_OFFSET_PC, in0 208 add loc25 = CONTEXT_OFFSET_B1, in0 209 add loc26 = CONTEXT_OFFSET_B2, in0 210 add loc27 = CONTEXT_OFFSET_B3, in0 211 add loc28 = CONTEXT_OFFSET_B4, in0 212 add loc29 = CONTEXT_OFFSET_B5, in0 213 214 add loc30 = CONTEXT_OFFSET_PR, in0 215 216 add loc31 = CONTEXT_OFFSET_F2, in0 217 add loc32 = CONTEXT_OFFSET_F3, in0 218 add loc33 = CONTEXT_OFFSET_F4, in0 219 add loc34 = CONTEXT_OFFSET_F5, in0 220 221 add loc35 = CONTEXT_OFFSET_F16, in0 222 add loc36 = CONTEXT_OFFSET_F17, in0 223 add loc37 = CONTEXT_OFFSET_F18, in0 224 add loc38 = CONTEXT_OFFSET_F19, in0 225 add loc39 = CONTEXT_OFFSET_F20, in0 226 add loc40 = CONTEXT_OFFSET_F21, in0 227 add loc41 = CONTEXT_OFFSET_F22, in0 228 add loc42 = CONTEXT_OFFSET_F23, in0 229 add loc43 = CONTEXT_OFFSET_F24, in0 230 add loc44 = CONTEXT_OFFSET_F25, in0 231 add loc45 = CONTEXT_OFFSET_F26, in0 232 add loc46 = CONTEXT_OFFSET_F27, in0 233 add loc47 = CONTEXT_OFFSET_F28, in0 234 add loc48 = CONTEXT_OFFSET_F29, in0 235 add loc49 = CONTEXT_OFFSET_F30, in0 236 add loc50 = CONTEXT_OFFSET_F31, in0 ;; 237 234 238 ld8 loc0 = [loc9] /* load ar.pfs */ 235 239 ld8 loc1 = [loc10] /* load ar.unat (caller) */ … … 239 243 ld8 loc5 = [loc14] /* load ar.rnat */ 240 244 ld8 loc6 = [loc15] /* load ar.lc */ 245 ld8 loc7 = [loc16] /* load ar.fpsr */ 241 246 242 247 .auto … … 269 274 mov ar.pfs = loc0 270 275 mov ar.rsc = loc3 276 mov ar.fpsr = loc7 271 277 272 278 .explicit … … 278 284 * Restore general registers including NaT bits 279 285 */ 280 ld8.fill r1 = [loc1 6] ;;281 ld8.fill r4 = [loc1 7] ;;282 ld8.fill r5 = [loc1 8] ;;283 ld8.fill r6 = [loc 19] ;;284 ld8.fill r7 = [loc2 0] ;;285 ld8.fill r12 = [loc2 1] ;; /* restore sp */286 ld8.fill r13 = [loc2 2] ;;286 ld8.fill r1 = [loc17] ;; 287 ld8.fill r4 = [loc18] ;; 288 ld8.fill r5 = [loc19] ;; 289 ld8.fill r6 = [loc20] ;; 290 ld8.fill r7 = [loc21] ;; 291 ld8.fill r12 = [loc22] ;; /* restore sp */ 292 ld8.fill r13 = [loc23] ;; 287 293 288 294 /* 289 295 * Restore branch registers 290 296 */ 291 ld8 loc2 = [loc2 3] /* restore pc */292 ld8 loc3 = [loc2 4]293 ld8 loc4 = [loc2 5]294 ld8 loc5 = [loc2 6]295 ld8 loc6 = [loc2 7]296 ld8 loc7 = [loc2 8] ;;297 ld8 loc2 = [loc24] /* restore pc */ 298 ld8 loc3 = [loc25] 299 ld8 loc4 = [loc26] 300 ld8 loc5 = [loc27] 301 ld8 loc6 = [loc28] 302 ld8 loc7 = [loc29] ;; 297 303 mov b0 = loc2 298 304 mov b1 = loc3 … … 305 311 * Restore predicate registers 306 312 */ 307 ld8 loc2 = [loc 29] ;;313 ld8 loc2 = [loc30] ;; 308 314 mov pr = loc2, ~0 309 315 … … 311 317 * Restore floating-point registers. 312 318 */ 313 ldf.fill f2 = [loc3 0]314 ldf.fill f3 = [loc3 1]315 ldf.fill f4 = [loc3 2]316 ldf.fill f5 = [loc3 3]317 318 ldf.fill f16 = [loc3 4]319 ldf.fill f17 = [loc3 5]320 ldf.fill f18 = [loc3 6]321 ldf.fill f19 = [loc3 7]322 ldf.fill f20 = [loc3 8]323 ldf.fill f21 = [loc 39]324 ldf.fill f22 = [loc4 0]325 ldf.fill f23 = [loc4 1]326 ldf.fill f24 = [loc4 2]327 ldf.fill f25 = [loc4 3]328 ldf.fill f26 = [loc4 4]329 ldf.fill f27 = [loc4 5]330 ldf.fill f28 = [loc4 6]331 ldf.fill f29 = [loc4 7]332 ldf.fill f30 = [loc4 8]333 ldf.fill f31 = [loc 49]319 ldf.fill f2 = [loc31] 320 ldf.fill f3 = [loc32] 321 ldf.fill f4 = [loc33] 322 ldf.fill f5 = [loc34] 323 324 ldf.fill f16 = [loc35] 325 ldf.fill f17 = [loc36] 326 ldf.fill f18 = [loc37] 327 ldf.fill f19 = [loc38] 328 ldf.fill f20 = [loc39] 329 ldf.fill f21 = [loc40] 330 ldf.fill f22 = [loc41] 331 ldf.fill f23 = [loc42] 332 ldf.fill f24 = [loc43] 333 ldf.fill f25 = [loc44] 334 ldf.fill f26 = [loc45] 335 ldf.fill f27 = [loc46] 336 ldf.fill f28 = [loc47] 337 ldf.fill f29 = [loc48] 338 ldf.fill f30 = [loc49] 339 ldf.fill f31 = [loc50] 334 340 335 341 mov ar.unat = loc1 -
kernel/arch/ia64/src/fpu_context.c
r0c27956 r7cd7a8d 462 462 void fpu_enable(void) 463 463 { 464 uint64_t a = 0;465 466 464 asm volatile ( 467 465 "rsm %0 ;;" … … 471 469 : "i" (PSR_DFH_MASK) 472 470 ); 473 474 asm volatile (475 "mov %0 = ar.fpsr ;;\n"476 "or %0 = %0,%1 ;;\n"477 "mov ar.fpsr = %0 ;;\n"478 : "+r" (a)479 : "r" (0x38)480 );481 471 } 482 472 483 473 void fpu_disable(void) 484 474 { 485 uint64_t a = 0;486 487 475 asm volatile ( 488 476 "ssm %0 ;;\n" … … 492 480 : "i" (PSR_DFH_MASK) 493 481 ); 482 } 483 484 void fpu_init(void) 485 { 486 uint64_t a = 0; 494 487 495 488 asm volatile ( … … 498 491 "mov ar.fpsr = %0 ;;\n" 499 492 : "+r" (a) 500 : "r" (0x38) 501 ); 502 } 503 504 void fpu_init(void) 505 { 506 uint64_t a = 0; 507 508 asm volatile ( 509 "mov %0 = ar.fpsr ;;\n" 510 "or %0 = %0,%1 ;;\n" 511 "mov ar.fpsr = %0 ;;\n" 512 : "+r" (a) 513 : "r" (0x38) 493 : "r" (FPSR_TRAPS_ALL) 514 494 ); 515 495
Note:
See TracChangeset
for help on using the changeset viewer.
