Index: kernel/arch/arm32/include/arch/context_struct.h
===================================================================
--- kernel/arch/arm32/include/arch/context_struct.h	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/include/arch/context_struct.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -34,5 +34,6 @@
 // XXX: This struct must match assembly code in src/context.S
 
-/* Thread context containing registers that must be preserved across
+/*
+ * Thread context containing registers that must be preserved across
  * function calls.
  */
Index: kernel/arch/arm32/include/arch/fpu_context.h
===================================================================
--- kernel/arch/arm32/include/arch/fpu_context.h	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/include/arch/fpu_context.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -42,5 +42,6 @@
 #define FPU_CONTEXT_ALIGN    8
 
-/* ARM Architecture reference manual, p B-1529.
+/*
+ * ARM Architecture reference manual, p B-1529.
  */
 typedef struct {
Index: kernel/arch/arm32/include/arch/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -64,5 +64,6 @@
 	unsigned should_be_zero : 1;
 
-	/* Pointer to the coarse 2nd level page table (holding entries for small
+	/*
+	 * Pointer to the coarse 2nd level page table (holding entries for small
 	 * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
 	 * tables that may hold even tiny pages (1KB) but they are bigger (4KB
@@ -80,6 +81,8 @@
 	unsigned cacheable : 1;
 
-	/* access permissions for each of 4 subparts of a page
-	 * (for each 1KB when small pages used */
+	/*
+	 * access permissions for each of 4 subparts of a page
+	 * (for each 1KB when small pages used
+	 */
 	unsigned access_permission_0 : 2;
 	unsigned access_permission_1 : 2;
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -66,5 +66,6 @@
 	unsigned should_be_zero_1 : 1;
 
-	/* Pointer to the coarse 2nd level page table (holding entries for small
+	/*
+	 * Pointer to the coarse 2nd level page table (holding entries for small
 	 * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
 	 * tables that may hold even tiny pages (1KB) but they are bigger (4KB
@@ -279,6 +280,8 @@
 	}
 
-	/* Shareable is ignored for devices (non-cacheable),
-	 * turn it off for normal memory. */
+	/*
+	 * Shareable is ignored for devices (non-cacheable),
+	 * turn it off for normal memory.
+	 */
 	p->shareable = 0;
 
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -147,13 +147,18 @@
 	/* Unaligned access is supported on armv6+ */
 #if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-	/* Enable unaligned access, RAZ/WI prior to armv6
+	/*
+	 * Enable unaligned access, RAZ/WI prior to armv6
 	 * switchable on armv6, RAO/WI writes on armv7,
 	 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
-	 * L.3.1 (p. 2456) */
+	 * L.3.1 (p. 2456)
+	 */
 	control_reg |= SCTLR_UNALIGNED_EN_FLAG;
-	/* Disable alignment checks, this turns unaligned access to undefined,
-	 * unless U bit is set. */
+	/*
+	 * Disable alignment checks, this turns unaligned access to undefined,
+	 * unless U bit is set.
+	 */
 	control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
-	/* Enable caching, On arm prior to armv7 there is only one level
+	/*
+	 * Enable caching, On arm prior to armv7 there is only one level
 	 * of caches. Data cache is coherent.
 	 * "This means that the behavior of accesses from the same observer to
@@ -169,5 +174,6 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-	/* ICache coherency is elaborated on in barrier.h.
+	/*
+	 * ICache coherency is elaborated on in barrier.h.
 	 * VIPT and PIPT caches need maintenance only on code modify,
 	 * so it should be safe for general use.
Index: kernel/arch/arm32/src/exception.c
===================================================================
--- kernel/arch/arm32/src/exception.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/src/exception.c	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -66,5 +66,6 @@
 static void install_handler(unsigned handler_addr, unsigned *vector)
 {
-	/* relative address (related to exc. vector) of the word
+	/*
+	 * Relative address (related to exc. vector) of the word
 	 * where handler's address is stored
 	 */
@@ -72,9 +73,9 @@
 	    PREFETCH_OFFSET;
 
-	/* make it LDR instruction and store at exception vector */
+	/* Make it LDR instruction and store at exception vector */
 	*vector = handler_address_ptr | LDR_OPCODE;
 	smc_coherence(vector);
 
-	/* store handler's address */
+	/* Store handler's address */
 	*(vector + EXC_VECTORS) = handler_addr;
 
Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -106,6 +106,8 @@
 	omap_irc_init(beagleboard.irc_addr);
 
-	/* Initialize timer. Use timer1, because it is in WKUP power domain
-	 * (always on) and has special capabilities for precise 1ms ticks */
+	/*
+	 * Initialize timer. Use timer1, because it is in WKUP power domain
+	 * (always on) and has special capabilities for precise 1ms ticks
+	 */
 	amdm37x_gpt_timer_ticks_init(&beagleboard.timer,
 	    AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ);
@@ -161,5 +163,6 @@
 	}
 	/** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
-	 * of ISR. DO this to avoid strange behavior. */
+	 * of ISR. DO this to avoid strange behavior.
+	 */
 	omap_irc_irq_ack(beagleboard.irc_addr);
 }
Index: kernel/arch/arm32/src/mm/page_fault.c
===================================================================
--- kernel/arch/arm32/src/mm/page_fault.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/arm32/src/mm/page_fault.c	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -153,6 +153,8 @@
 	}
 
-	/* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
-	 * A5.3 (PDF p. 206) */
+	/*
+	 * See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
+	 * A5.3 (PDF p. 206)
+	 */
 	static const struct {
 		uint32_t mask;