Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
@@ -147,13 +147,18 @@
 	/* Unaligned access is supported on armv6+ */
 #if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-	/* Enable unaligned access, RAZ/WI prior to armv6
+	/*
+	 * Enable unaligned access, RAZ/WI prior to armv6
 	 * switchable on armv6, RAO/WI writes on armv7,
 	 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
-	 * L.3.1 (p. 2456) */
+	 * L.3.1 (p. 2456)
+	 */
 	control_reg |= SCTLR_UNALIGNED_EN_FLAG;
-	/* Disable alignment checks, this turns unaligned access to undefined,
-	 * unless U bit is set. */
+	/*
+	 * Disable alignment checks, this turns unaligned access to undefined,
+	 * unless U bit is set.
+	 */
 	control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
-	/* Enable caching, On arm prior to armv7 there is only one level
+	/*
+	 * Enable caching, On arm prior to armv7 there is only one level
 	 * of caches. Data cache is coherent.
 	 * "This means that the behavior of accesses from the same observer to
@@ -169,5 +174,6 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-	/* ICache coherency is elaborated on in barrier.h.
+	/*
+	 * ICache coherency is elaborated on in barrier.h.
 	 * VIPT and PIPT caches need maintenance only on code modify,
 	 * so it should be safe for general use.