Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision 15187c3fe0f95b19837cde4c7f8b673cd31919c6)
+++ boot/arch/arm32/src/mm.c	(revision 7bf921771914b9adbd576a885dc72f248d68883d)
@@ -147,8 +147,7 @@
 	 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
 	 */
-	//TODO: Use write-back write-allocate caches
-	pte->tex = section_cacheable(frame) ? 6 : 0;
-	pte->bufferable = section_cacheable(frame) ? 0 : 0;
-	pte->cacheable = section_cacheable(frame) ? 1 : 0;
+	pte->tex = section_cacheable(frame) ? 5 : 0;
+	pte->cacheable = section_cacheable(frame) ? 0 : 0;
+	pte->bufferable = section_cacheable(frame) ? 1 : 0;
 #else
 	pte->bufferable = 1;
@@ -184,5 +183,5 @@
 	 */
 	uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
-	val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+	val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
 	TTBR0_write(val);
 }
Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision 15187c3fe0f95b19837cde4c7f8b673cd31919c6)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision 7bf921771914b9adbd576a885dc72f248d68883d)
@@ -154,5 +154,5 @@
 {
 	uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
-	val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+	val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
 	TTBR0_write(val);
 }
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 15187c3fe0f95b19837cde4c7f8b673cd31919c6)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 7bf921771914b9adbd576a885dc72f248d68883d)
@@ -265,8 +265,7 @@
 		 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
 		 */
-		//TODO: Use writeback, write-allocate caches
-		p->tex = 6;
-		p->cacheable = 1;
-		p->bufferable = 0;
+		p->tex = 5;
+		p->cacheable = 0;
+		p->bufferable = 1;
 	} else {
 		/*