Index: arch/ia32/src/cpu/cpu.c
===================================================================
--- arch/ia32/src/cpu/cpu.c	(revision 43114c515872442297f5b1b8a327743ef24c825a)
+++ arch/ia32/src/cpu/cpu.c	(revision 7b7d7d1cbbddea9be6f0e75c0adabf7bda19ad53)
@@ -35,4 +35,6 @@
 #include <print.h>
 #include <typedefs.h>
+
+#include <arch/smp/apic.h>
 
 /*
Index: arch/ia32/src/pm.c
===================================================================
--- arch/ia32/src/pm.c	(revision 43114c515872442297f5b1b8a327743ef24c825a)
+++ arch/ia32/src/pm.c	(revision 7b7d7d1cbbddea9be6f0e75c0adabf7bda19ad53)
@@ -67,5 +67,5 @@
 
 /* gdtr changes everytime new CPU is initialized */
-struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
+struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = (__address) gdt };
 struct ptr_16_32 idtr = { .limit = sizeof(idt), .base = (__address) idt };
 
Index: arch/ia32/src/smp/apic.c
===================================================================
--- arch/ia32/src/smp/apic.c	(revision 43114c515872442297f5b1b8a327743ef24c825a)
+++ arch/ia32/src/smp/apic.c	(revision 7b7d7d1cbbddea9be6f0e75c0adabf7bda19ad53)
@@ -27,6 +27,4 @@
  */
 
-#ifdef __SMP__
-
 #include <arch/types.h>
 #include <arch/smp/apic.h>
@@ -39,4 +37,6 @@
 #include <arch/asm.h>
 #include <arch.h>
+
+#ifdef __SMP__
 
 /*
@@ -222,5 +222,17 @@
 {
 	__u32 tmp, t1, t2;
-	
+	int cpu_id = config.cpu_active - 1;
+	
+
+	/*
+	 * Here we set local APIC ID's so that they match operating system's CPU ID's
+	 * This operation is dangerous as it is model specific.
+	 * TODO: some care should be taken.
+	 * NOTE: CPU may not be used to define APIC ID
+	 */
+	if (l_apic_id() != cpu_id) {
+		l_apic[L_APIC_ID] &= L_APIC_IDClear;
+		l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift);
+	}
 
 	l_apic[LVT_Err] |= (1<<16);
@@ -271,5 +283,5 @@
 	int i, lint;
 
-	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf);
+	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
 	printf("LVT_Tm: ");
@@ -305,5 +317,5 @@
 	 * This register is supported only on P6 and higher.
 	 */
-	if (CPU->family > 5) {
+	if (CPU->arch.family > 5) {
 		printf("LVT_PCINT: ");
 		if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
@@ -324,4 +336,9 @@
 	l_apic_eoi();
 	clock();
+}
+
+__u8 l_apic_id(void)
+{
+	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
 }