Index: boot/arch/ppc32/loader/asm.S
===================================================================
--- boot/arch/ppc32/loader/asm.S	(revision 34259b90806e6f0531d76a3687420f3ed458b76b)
+++ boot/arch/ppc32/loader/asm.S	(revision 7b187ef6f8a1aeda140487a35c3664962045e88c)
@@ -30,9 +30,21 @@
 #include "regname.h"
 
-.macro FLUSH_CACHE addr
+.macro SMC_COHERENCY addr
 	dcbst 0, \addr
 	sync
 	icbi 0, \addr
+	sync
 	isync
+.endm
+
+.macro FLUSH_DCACHE addr
+	dcbst 0, \addr
+	sync
+	isync
+.endm
+
+.macro TLB_FLUSH reg
+	tlbie \reg
+	addi \reg, \reg, 0x1000
 .endm
 
@@ -172,5 +184,5 @@
 			stw r28, 0(r30)
 			
-			FLUSH_CACHE r30
+			SMC_COHERENCY r30
 			
 			addi r29, r29, 4
@@ -269,5 +281,5 @@
 		
 		stw r29, 0(r31)
-		FLUSH_CACHE r31
+		FLUSH_DCACHE r31
 		
 		addi r31, r31, 4
@@ -329,5 +341,84 @@
 #endif
 	
+	# flush TLB
+	
+	li r31, 0
+	sync
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	TLB_FLUSH r31
+	
+	eieio
 	tlbsync
+	sync
 	
 	# start the kernel
Index: boot/arch/ppc32/loader/regname.h
===================================================================
--- boot/arch/ppc32/loader/regname.h	(revision 34259b90806e6f0531d76a3687420f3ed458b76b)
+++ boot/arch/ppc32/loader/regname.h	(revision 7b187ef6f8a1aeda140487a35c3664962045e88c)
@@ -218,4 +218,5 @@
 #define hid0_icfi	(1 << 11)
 #define hid0_dci	(1 << 10)
+#define hid0_sten	(1 << 7)
 
 #endif
Index: kernel/arch/ppc32/include/asm/regname.h
===================================================================
--- kernel/arch/ppc32/include/asm/regname.h	(revision 34259b90806e6f0531d76a3687420f3ed458b76b)
+++ kernel/arch/ppc32/include/asm/regname.h	(revision 7b187ef6f8a1aeda140487a35c3664962045e88c)
@@ -225,4 +225,5 @@
 #define hid0_icfi	(1 << 11)
 #define hid0_dci	(1 << 10)
+#define hid0_sten	(1 << 7)
 
 #endif
Index: kernel/arch/ppc32/include/barrier.h
===================================================================
--- kernel/arch/ppc32/include/barrier.h	(revision 34259b90806e6f0531d76a3687420f3ed458b76b)
+++ kernel/arch/ppc32/include/barrier.h	(revision 7b187ef6f8a1aeda140487a35c3664962045e88c)
@@ -56,4 +56,5 @@
 		"sync\n"
 		"icbi 0, %0\n"
+		"sync\n"
 		"isync\n"
 		:: "r" (addr)
@@ -77,5 +78,8 @@
 	}
 
-	asm volatile ("isync");
+	asm volatile (
+		"sync\n"
+		"isync\n"
+	);
 }
 
Index: kernel/arch/ppc32/src/mm/tlb.c
===================================================================
--- kernel/arch/ppc32/src/mm/tlb.c	(revision 34259b90806e6f0531d76a3687420f3ed458b76b)
+++ kernel/arch/ppc32/src/mm/tlb.c	(revision 7b187ef6f8a1aeda140487a35c3664962045e88c)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ppc32mm	
+/** @addtogroup ppc32mm
  * @{
  */
@@ -46,4 +46,9 @@
 static unsigned int seed = 10;
 static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
+
+
+#define TLB_FLUSH \
+	"tlbie %0\n" \
+	"addi %0, %0, 0x1000\n"
 
 
@@ -412,6 +417,85 @@
 void tlb_invalidate_all(void)
 {
-	asm volatile (
+	uint32_t index;
+	asm volatile (
+		"li %0, 0\n"
+		"sync\n"
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		TLB_FLUSH
+		
+		"eieio\n"
 		"tlbsync\n"
+		"sync\n"
+		: "=r" (index)
 	);
 }