Index: arch/mips32/include/exception.h =================================================================== --- arch/mips32/include/exception.h (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/include/exception.h (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -95,3 +95,4 @@ extern void exception_entry(void); extern void cache_error_entry(void); +extern void exception_init(void); #endif Index: arch/mips32/include/interrupt.h =================================================================== --- arch/mips32/include/interrupt.h (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/include/interrupt.h (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -32,5 +32,8 @@ #include -#define IVT_ITEMS 8 +#define IVT_ITEMS 40 +#define INT_OFFSET 32 + +#define int_register(it, name, handler) exc_register(((it)+INT_OFFSET),name,handler) #define IRQ2 2 @@ -40,5 +43,4 @@ #define TIMER_IRQ IRQ7 -extern void interrupt(struct exception_regdump *pstate); extern void interrupt_init(void); Index: arch/mips32/src/drivers/arc.c =================================================================== --- arch/mips32/src/drivers/arc.c (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/src/drivers/arc.c (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -252,5 +252,5 @@ chardev_initialize("arc_console", &console, &arc_ops); - old_timer = exc_register(TIMER_IRQ, "arc_kb_poll", timer_replace); + old_timer = int_register(TIMER_IRQ, "arc_kb_poll", timer_replace); return &console; } Index: arch/mips32/src/drivers/msim.c =================================================================== --- arch/mips32/src/drivers/msim.c (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/src/drivers/msim.c (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -82,5 +82,5 @@ chardev_initialize("msim_console", &console, &msim_ops); - exc_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); + int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); cp0_unmask_int(MSIM_KBD_IRQ); Index: arch/mips32/src/drivers/serial.c =================================================================== --- arch/mips32/src/drivers/serial.c (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/src/drivers/serial.c (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -112,9 +112,9 @@ kb_enabled = true; -// exc_register(2, "serial_drvr", serial_interrupt); +// int_register(2, "serial_drvr", serial_interrupt); /* I don't know why, but the serial interrupts simply * don't work on simics */ - old_timer = exc_register(TIMER_IRQ, "serial_drvr_poll", timer_replace); + old_timer = int_register(TIMER_IRQ, "serial_drvr_poll", timer_replace); Index: arch/mips32/src/exception.c =================================================================== --- arch/mips32/src/exception.c (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/src/exception.c (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -35,4 +35,94 @@ #include #include +#include +#include +#include + +static char * exctable[] = { + "Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store", + "Address Error - load/instr. fetch", + "Address Error - store", + "Bus Error - fetch instruction", + "Bus Error - data reference", + "Syscall", + "BreakPoint", + "Reserved Instruction", + "Coprocessor Unusable", + "Arithmetic Overflow", + "Trap", + "Virtual Coherency - instruction", + "Floating Point", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "WatchHi/WatchLo", /* 23 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "Virtual Coherency - data", +}; + +static void print_regdump(struct exception_regdump *pstate) +{ + char *pcsymbol = ""; + char *rasymbol = ""; + + char *s = get_symtab_entry(pstate->epc); + if (s) + pcsymbol = s; + s = get_symtab_entry(pstate->ra); + if (s) + rasymbol = s; + + printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, + pstate->ra,rasymbol); +} + +static void unhandled_exception(int n, void *data) +{ + struct exception_regdump *pstate = (struct exception_regdump *)data; + + print_regdump(pstate); + panic("unhandled exception %s\n", exctable[n]); +} + +static void breakpoint_exception(int n, void *data) +{ + struct exception_regdump *pstate = (struct exception_regdump *)data; + /* it is necessary to not re-execute BREAK instruction after + returning from Exception handler + (see page 138 in R4000 Manual for more information) */ + pstate->epc += 4; +} + +static void tlbmod_exception(int n, void *data) +{ + struct exception_regdump *pstate = (struct exception_regdump *)data; + tlb_modified(pstate); +} + +static void tlbinv_exception(int n, void *data) +{ + struct exception_regdump *pstate = (struct exception_regdump *)data; + tlb_invalid(pstate); +} + +static void cpunsbl_exception(int n, void *data) +{ + if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) + scheduler_fpu_lazy_request(); + else + panic("unhandled Coprocessor Unusable Exception\n"); +} + +static void interrupt_exception(int n, void *pstate) +{ + __u32 cause; + int i; + + /* decode interrupt number and process the interrupt */ + cause = (cp0_cause_read() >> 8) &0xff; + + for (i = 0; i < 8; i++) + if (cause & (1 << i)) + exc_dispatch(i+INT_OFFSET, pstate); +} + void exception(struct exception_regdump *pstate) @@ -64,67 +154,7 @@ cause = cp0_cause_read(); excno = cp0_cause_excno(cause); - /* decode exception number and process the exception */ - switch (excno) { - case EXC_Int: - interrupt(pstate); - break; - case EXC_TLBL: - case EXC_TLBS: - tlb_invalid(pstate); - break; - case EXC_CpU: -#ifdef CONFIG_FPU_LAZY - if (cp0_cause_coperr(cause) == fpu_cop_id) - scheduler_fpu_lazy_request(); - else -#endif - panic("unhandled Coprocessor Unusable Exception\n"); - break; - case EXC_Mod: - tlb_modified(pstate); - break; - case EXC_AdEL: - panic("unhandled Address Error Exception - load or instruction fetch\n"); - break; - case EXC_AdES: - panic("unhandled Address Error Exception - store\n"); - break; - case EXC_IBE: - panic("unhandled Bus Error Exception - fetch instruction\n"); - break; - case EXC_DBE: - panic("unhandled Bus Error Exception - data reference: load or store\n"); - break; - case EXC_Bp: - /* it is necessary to not re-execute BREAK instruction after returning from Exception handler - (see page 138 in R4000 Manual for more information) */ - epc_shift = 4; - break; - case EXC_RI: - panic("unhandled Reserved Instruction Exception\n"); - break; - case EXC_Ov: - panic("unhandled Arithmetic Overflow Exception\n"); - break; - case EXC_Tr: - panic("unhandled Trap Exception\n"); - break; - case EXC_VCEI: - panic("unhandled Virtual Coherency Exception - instruction\n"); - break; - case EXC_FPE: - panic("unhandled Floating-Point Exception\n"); - break; - case EXC_WATCH: - panic("unhandled reference to WatchHi/WatchLo address\n"); - break; - case EXC_VCED: - panic("unhandled Virtual Coherency Exception - data\n"); - break; - default: - panic("unhandled exception %d\n", excno); - } - - pstate->epc += epc_shift; + /* Dispatch exception */ + exc_dispatch(excno, pstate); + /* Set to NULL, so that we can still support nested * exceptions @@ -136,2 +166,19 @@ THREAD->pstate = NULL; } + +void exception_init(void) +{ + int i; + + /* Clear exception table */ + for (i=0;i < IVT_ITEMS; i++) + exc_register(i, "undef", unhandled_exception); + exc_register(EXC_Bp, "bkpoint", breakpoint_exception); + exc_register(EXC_Mod, "tlb_mod", tlbmod_exception); + exc_register(EXC_TLBL, "tlbinvl", tlbinv_exception); + exc_register(EXC_TLBS, "tlbinvl", tlbinv_exception); + exc_register(EXC_Int, "interrupt", interrupt_exception); +#ifdef CONFIG_FPU_LAZY + exc_register(EXC_CpU, "cpunus", cpun_exception); +#endif +} Index: arch/mips32/src/interrupt.c =================================================================== --- arch/mips32/src/interrupt.c (revision e5fcf00b5dfb672f010204b557cacad3c4dbc22f) +++ arch/mips32/src/interrupt.c (revision 7a8c866a8ae0f53b6de307a56f01c3c70e10bbd7) @@ -33,24 +33,5 @@ #include #include