Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
+++ kernel/arch/sparc64/include/barrier.h	(revision 7a4202dd73f7bb539689bd5daa846b77584b939e)
@@ -61,6 +61,6 @@
 	asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
 
-/** Flush Instruction Memory instruction. */
-static inline void flush_blind(void)
+/** Flush Instruction pipeline. */
+static inline void flush_pipeline(void)
 {
 	/*
Index: kernel/arch/sparc64/include/mm/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/tlb.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
+++ kernel/arch/sparc64/include/mm/tlb.h	(revision 7a4202dd73f7bb539689bd5daa846b77584b939e)
@@ -161,5 +161,5 @@
 {
 	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
-	flush_blind();
+	flush_pipeline();
 }
 
@@ -180,5 +180,5 @@
 {
 	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
-	flush_blind();
+	flush_pipeline();
 }
 
@@ -210,5 +210,5 @@
 	reg.tlb_entry = entry;
 	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-	flush_blind();
+	flush_pipeline();
 }
 
@@ -280,5 +280,5 @@
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
-	flush_blind();
+	flush_pipeline();
 }
 
@@ -319,5 +319,5 @@
 {
 	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
-	flush_blind();
+	flush_pipeline();
 }
 
@@ -348,5 +348,5 @@
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
-	flush_blind();
+	flush_pipeline();
 }
 
@@ -401,5 +401,5 @@
 							 * address within the
 							 * ASI */ 
-	flush_blind();
+	flush_pipeline();
 }