Index: kernel/arch/arm32/include/cp15.h
===================================================================
--- kernel/arch/arm32/include/cp15.h	(revision 9043e7e036777c3fb0a0a0d7482f60a5dd29e2ae)
+++ kernel/arch/arm32/include/cp15.h	(revision 7a38962632e530967be4d27ffab7f9f38716b7f6)
@@ -83,6 +83,6 @@
 	CTR_I_MIN_LINE_SHIFT = 0,
 	CTR_L1I_POLICY_MASK = 0x0000c000,
-	VTR_L1I_POLICY_AIVIVT = 0x00004000,
-	VTR_L1I_POLICY_VIPT = 0x00008000,
+	CTR_L1I_POLICY_AIVIVT = 0x00004000,
+	CTR_L1I_POLICY_VIPT = 0x00008000,
 	CTR_L1I_POLICY_PIPT = 0x0000c000,
 	/* ARMv6 format */
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 9043e7e036777c3fb0a0a0d7482f60a5dd29e2ae)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 7a38962632e530967be4d27ffab7f9f38716b7f6)
@@ -151,15 +151,20 @@
 	 *    B3.11.1 (p. 1383)
 	 * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
-	 * L2 Cache for armv7 was enabled in boot code.
+	 * L2 Cache for armv7 is enabled by default (i.e. controlled by
+	 * this flag).
 	 */
 	control_reg |= SCTLR_CACHE_EN_FLAG;
 #endif
-#ifdef PROCESSOR_cortex_a8
+#ifdef PROCESSOR_ARCH_armv7_a
 	 /* ICache coherency is elaborate on in barrier.h.
-	  * Cortex-A8 implements IVIPT extension.
-	  * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
-	control_reg |= SCTLR_INST_CACHE_EN_FLAG;
-	/* Enable branch prediction RAZ/WI if not supported */
-	control_reg |= SCTLR_BRANCH_PREDICT_EN_FLAG;
+	  * VIPT and PIPT caches need maintenance only on code modify,
+	  * so it should be safe for general use.
+	  * Enable branch predictors too as they follow the same rules
+	  * as ICache and they can be flushed together
+	  */
+	if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
+		control_reg |=
+		    SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
+	}
 #endif
 	SCTLR_write(control_reg);