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  • kernel/arch/abs32le/include/atomic.h

    r50fda24 r7a0359b  
    3636#define KERN_abs32le_ATOMIC_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <arch/barrier.h>
    4040#include <preemption.h>
     41#include <verify.h>
     42#include <trace.h>
    4143
    42 static inline void atomic_inc(atomic_t *val) {
     44NO_TRACE ATOMIC static inline void atomic_inc(atomic_t *val)
     45    WRITES(&val->count)
     46    REQUIRES_EXTENT_MUTABLE(val)
     47    REQUIRES(val->count < ATOMIC_COUNT_MAX)
     48{
    4349        /* On real hardware the increment has to be done
    4450           as an atomic action. */
    … …  
    4753}
    4854
    49 static inline void atomic_dec(atomic_t *val) {
     55NO_TRACE ATOMIC static inline void atomic_dec(atomic_t *val)
     56    WRITES(&val->count)
     57    REQUIRES_EXTENT_MUTABLE(val)
     58    REQUIRES(val->count > ATOMIC_COUNT_MIN)
     59{
    5060        /* On real hardware the decrement has to be done
    5161           as an atomic action. */
    5262       
    53         val->count++;
     63        val->count--;
    5464}
    5565
    56 static inline long atomic_postinc(atomic_t *val)
     66NO_TRACE ATOMIC static inline atomic_count_t atomic_postinc(atomic_t *val)
     67    WRITES(&val->count)
     68    REQUIRES_EXTENT_MUTABLE(val)
     69    REQUIRES(val->count < ATOMIC_COUNT_MAX)
    5770{
    5871        /* On real hardware both the storing of the previous
    … …  
    6073           atomic action. */
    6174       
    62         long prev = val->count;
     75        atomic_count_t prev = val->count;
    6376       
    6477        val->count++;
    … …  
    6679}
    6780
    68 static inline long atomic_postdec(atomic_t *val)
     81NO_TRACE ATOMIC static inline atomic_count_t atomic_postdec(atomic_t *val)
     82    WRITES(&val->count)
     83    REQUIRES_EXTENT_MUTABLE(val)
     84    REQUIRES(val->count > ATOMIC_COUNT_MIN)
    6985{
    7086        /* On real hardware both the storing of the previous
    … …  
    7288           atomic action. */
    7389       
    74         long prev = val->count;
     90        atomic_count_t prev = val->count;
    7591       
    7692        val->count--;
    … …  
    8197#define atomic_predec(val)  (atomic_postdec(val) - 1)
    8298
    83 static inline uint32_t test_and_set(atomic_t *val) {
    84         uint32_t v;
     99NO_TRACE ATOMIC static inline atomic_count_t test_and_set(atomic_t *val)
     100    WRITES(&val->count)
     101    REQUIRES_EXTENT_MUTABLE(val)
     102{
     103        /* On real hardware the retrieving of the original
     104           value and storing 1 have to be done as a single
     105           atomic action. */
    85106       
    86         asm volatile (
    87                 "movl $1, %[v]\n"
    88                 "xchgl %[v], %[count]\n"
    89                 : [v] "=r" (v), [count] "+m" (val->count)
    90         );
    91        
    92         return v;
     107        atomic_count_t prev = val->count;
     108        val->count = 1;
     109        return prev;
    93110}
    94111
    95 /** ia32 specific fast spinlock */
    96 static inline void atomic_lock_arch(atomic_t *val)
     112NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
     113    WRITES(&val->count)
     114    REQUIRES_EXTENT_MUTABLE(val)
    97115{
    98         uint32_t tmp;
    99        
    100         preemption_disable();
    101         asm volatile (
    102                 "0:\n"
    103                 "pause\n"        /* Pentium 4's HT love this instruction */
    104                 "mov %[count], %[tmp]\n"
    105                 "testl %[tmp], %[tmp]\n"
    106                 "jnz 0b\n"       /* lightweight looping on locked spinlock */
    107                
    108                 "incl %[tmp]\n"  /* now use the atomic operation */
    109                 "xchgl %[count], %[tmp]\n"
    110                 "testl %[tmp], %[tmp]\n"
    111                 "jnz 0b\n"
    112                 : [count] "+m" (val->count), [tmp] "=&r" (tmp)
    113         );
    114         /*
    115          * Prevent critical section code from bleeding out this way up.
    116          */
    117         CS_ENTER_BARRIER();
     116        do {
     117                while (val->count);
     118        } while (test_and_set(val));
    118119}
    119120
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