Index: uspace/drv/nic/e1k/e1k.c =================================================================== --- uspace/drv/nic/e1k/e1k.c (revision c520034c1c09f379852efaec5da361fb0a910b01) +++ uspace/drv/nic/e1k/e1k.c (revision 77c2b027811f1f4abd6702b92df846515c88cad4) @@ -44,4 +44,5 @@ #include #include +#include #include #include @@ -111,4 +112,7 @@ /** E1000 device data */ typedef struct { + /** Device configuration */ + e1000_info_t info; + /** Physical registers base address */ void *reg_base_phys; @@ -143,7 +147,4 @@ /** Used milticast Receive addrress count */ unsigned int multicast_ra_count; - - /** PCI device ID */ - uint16_t device_id; /** The irq assigned */ @@ -1888,19 +1889,71 @@ /* Allocate driver data for the device. */ e1000_t *e1000 = e1000_create_dev_data(dev); - if (e1000 == NULL) + if (e1000 == NULL) { + ddf_msg(LVL_ERROR, "Unable to allocate device softstate"); return ENOMEM; + } /* Obtain and fill hardware resources info */ int rc = e1000_get_resource_info(dev); if (rc != EOK) { + ddf_msg(LVL_ERROR, "Cannot obtain hardware resources"); e1000_dev_cleanup(dev); return rc; } + uint16_t device_id; rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID, - &e1000->device_id); + &device_id); if (rc != EOK) { + ddf_msg(LVL_ERROR, "Cannot access PCI configuration space"); e1000_dev_cleanup(dev); return rc; + } + + e1000_board_t board; + switch (device_id) { + case 0x1013: + case 0x1018: + case 0x1078: + board = E1000_82541; + break; + case 0x1076: + case 0x1077: + case 0x107c: + board = E1000_82541REV2; + break; + case 0x1019: + case 0x101a: + board = E1000_82547; + break; + case 0x10b9: + board = E1000_82572; + break; + case 0x1096: + board = E1000_80003ES2; + break; + default: + ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")", + device_id); + e1000_dev_cleanup(dev); + return ENOTSUP; + } + + switch (board) { + case E1000_82541: + case E1000_82541REV2: + case E1000_82572: + e1000->info.eerd_start = 0x01; + e1000->info.eerd_done = 0x10; + e1000->info.eerd_address_offset = 8; + e1000->info.eerd_data_offset = 16; + break; + case E1000_82547: + case E1000_80003ES2: + e1000->info.eerd_start = 0x01; + e1000->info.eerd_done = 0x02; + e1000->info.eerd_address_offset = 2; + e1000->info.eerd_data_offset = 16; + break; } @@ -2023,34 +2076,12 @@ fibril_mutex_lock(&e1000->eeprom_lock); - uint32_t eerd_done; - uint32_t eerd_address_offset; - - switch (e1000->device_id) { - case 0x107c: - case 0x1013: - case 0x1018: - case 0x1019: - case 0x101A: - case 0x1076: - case 0x1077: - case 0x1078: - case 0x10b9: - /* 82541xx and 82547GI/EI */ - eerd_done = EERD_DONE_82541XX_82547GI_EI; - eerd_address_offset = EERD_ADDRESS_OFFSET_82541XX_82547GI_EI; - break; - default: - eerd_done = EERD_DONE; - eerd_address_offset = EERD_ADDRESS_OFFSET; - break; - } - /* Write address and START bit to EERD register */ - uint32_t write_data = EERD_START | - (((uint32_t) eeprom_address) << eerd_address_offset); + uint32_t write_data = e1000->info.eerd_start | + (((uint32_t) eeprom_address) << + e1000->info.eerd_address_offset); E1000_REG_WRITE(e1000, E1000_EERD, write_data); uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD); - while ((eerd & eerd_done) == 0) { + while ((eerd & e1000->info.eerd_done) == 0) { usleep(1); eerd = E1000_REG_READ(e1000, E1000_EERD); @@ -2059,5 +2090,5 @@ fibril_mutex_unlock(&e1000->eeprom_lock); - return (uint16_t) (eerd >> EERD_DATA_OFFSET); + return (uint16_t) (eerd >> e1000->info.eerd_data_offset); } @@ -2228,4 +2259,7 @@ nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops, &e1000_nic_iface); + + ddf_log_init(NAME, LVL_ERROR); + ddf_msg(LVL_NOTE, "HelenOS E1000 driver started"); return ddf_driver_main(&e1000_driver); } Index: uspace/drv/nic/e1k/e1k.h =================================================================== --- uspace/drv/nic/e1k/e1k.h (revision c520034c1c09f379852efaec5da361fb0a910b01) +++ uspace/drv/nic/e1k/e1k.h (revision 77c2b027811f1f4abd6702b92df846515c88cad4) @@ -82,24 +82,41 @@ } e1000_tx_descriptor_t; +/** E1000 boards */ +typedef enum { + E1000_82541, + E1000_82541REV2, + E1000_82547, + E1000_82572, + E1000_80003ES2 +} e1000_board_t; + +typedef struct { + uint32_t eerd_start; + uint32_t eerd_done; + + uint32_t eerd_address_offset; + uint32_t eerd_data_offset; +} e1000_info_t; + /** VLAN tag bits */ -enum e1000_vlantag { +typedef enum { VLANTAG_CFI = (1 << 12), /**< Canonical Form Indicator */ -}; +} e1000_vlantag_t; /** Transmit descriptor COMMAND field bits */ -enum e1000_txdescriptor_command { +typedef enum { TXDESCRIPTOR_COMMAND_VLE = (1 << 6), /**< VLAN Packet Enable */ TXDESCRIPTOR_COMMAND_RS = (1 << 3), /**< Report Status */ TXDESCRIPTOR_COMMAND_IFCS = (1 << 1), /**< Insert FCS */ TXDESCRIPTOR_COMMAND_EOP = (1 << 0) /**< End Of Packet */ -}; +} e1000_txdescriptor_command_t; /** Transmit descriptor STATUS field bits */ -enum e1000_txdescriptor_status { +typedef enum { TXDESCRIPTOR_STATUS_DD = (1 << 0) /**< Descriptor Done */ -}; +} e1000_txdescriptor_status_t; /** E1000 Registers */ -enum e1000_registers { +typedef enum { E1000_CTRL = 0x0, /**< Device Control Register */ E1000_STATUS = 0x8, /**< Device Status Register */ @@ -130,24 +147,8 @@ E1000_IMS = 0xD0, /**< Interrupt Mask Set/Read Register */ E1000_IMC = 0xD8 /**< Interrupt Mask Clear Register */ -}; - -/** EEPROM Read Register fields */ -enum e1000_eerd { - /** Start Read */ - EERD_START = (1 << 0), - /** Read Done */ - EERD_DONE = (1 << 4), - /** Read Done for 82541xx and 82547GI/EI */ - EERD_DONE_82541XX_82547GI_EI = (1 << 1), - /** Read Address offset */ - EERD_ADDRESS_OFFSET = 8, - /** Read Address offset for 82541xx and 82547GI/EI */ - EERD_ADDRESS_OFFSET_82541XX_82547GI_EI = 2, - /** Read Data */ - EERD_DATA_OFFSET = 16 -}; +} e1000_registers_t; /** Device Control Register fields */ -enum e1000_ctrl { +typedef enum { CTRL_FD = (1 << 0), /**< Full-Duplex */ CTRL_LRST = (1 << 3), /**< Link Reset */ @@ -176,8 +177,8 @@ CTRL_VME = (1 << 30), /**< VLAN Mode Enable */ CTRL_PHY_RST = (1 << 31) /**< PHY Reset */ -}; +} e1000_ctrl_t; /** Device Status Register fields */ -enum e1000_status { +typedef enum { STATUS_FD = (1 << 0), /**< Link Full Duplex configuration Indication */ STATUS_LU = (1 << 1), /**< Link Up Indication */ @@ -197,5 +198,5 @@ /** Link speed setting 1000 Mb/s value variant B */ STATUS_SPEED_1000B = 3, -}; +} e1000_status_t; /** Transmit IPG Register fields @@ -204,31 +205,31 @@ * */ -enum e1000_tipg { +typedef enum { TIPG_IPGT_SHIFT = 0, /**< IPG Transmit Time shift */ TIPG_IPGR1_SHIFT = 10, /**< IPG Receive Time 1 */ TIPG_IPGR2_SHIFT = 20 /**< IPG Receive Time 2 */ -}; +} e1000_tipg_t; /** Transmit Control Register fields */ -enum e1000_tctl { +typedef enum { TCTL_EN = (1 << 1), /**< Transmit Enable */ TCTL_PSP = (1 << 3), /**< Pad Short Packets */ TCTL_CT_SHIFT = 4, /**< Collision Threshold shift */ TCTL_COLD_SHIFT = 12 /**< Collision Distance shift */ -}; +} e1000_tctl_t; /** ICR register fields */ -enum e1000_icr { +typedef enum { ICR_TXDW = (1 << 0), /**< Transmit Descriptor Written Back */ ICR_RXT0 = (1 << 7) /**< Receiver Timer Interrupt */ -}; +} e1000_icr_t; /** RAH register fields */ -enum e1000_rah { +typedef enum { RAH_AV = (1 << 31) /**< Address Valid */ -}; +} e1000_rah_t; /** RCTL register fields */ -enum e1000_rctl { +typedef enum { RCTL_EN = (1 << 1), /**< Receiver Enable */ RCTL_SBP = (1 << 2), /**< Store Bad Packets */ @@ -237,5 +238,5 @@ RCTL_BAM = (1 << 15), /**< Broadcast Accept Mode */ RCTL_VFE = (1 << 18) /**< VLAN Filter Enable */ -}; +} e1000_rctl_t; #endif Index: uspace/drv/nic/e1k/e1k.ma =================================================================== --- uspace/drv/nic/e1k/e1k.ma (revision c520034c1c09f379852efaec5da361fb0a910b01) +++ uspace/drv/nic/e1k/e1k.ma (revision 77c2b027811f1f4abd6702b92df846515c88cad4) @@ -22,5 +22,6 @@ 10 pci/ven=8086&dev=107b 10 pci/ven=8086&dev=107c +10 pci/ven=8086&dev=1096 +10 pci/ven=8086&dev=10b9 10 pci/ven=8086&dev=1107 10 pci/ven=8086&dev=1112 -10 pci/ven=8086&dev=10b9