Index: kernel/arch/ia32/src/drivers/i8254.c
===================================================================
--- kernel/arch/ia32/src/drivers/i8254.c	(revision 687c3cd5921e1d47b5311bdcf4dfbc5f55ee093b)
+++ kernel/arch/ia32/src/drivers/i8254.c	(revision 76dd25b7f1290f21230e4d3c41919e84f05bb9d8)
@@ -95,8 +95,8 @@
 void i8254_normal_operation(void)
 {
-	outb(CLK_PORT4, 0x36);
+	pio_write_8(CLK_PORT4, 0x36);
 	pic_disable_irqs(1 << IRQ_CLK);
-	outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
-	outb(CLK_PORT1, (CLK_CONST / HZ) >> 8);
+	pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
+	pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8);
 	pic_enable_irqs(1 << IRQ_CLK);
 }
@@ -115,34 +115,34 @@
 	 * MAGIC_NUMBER is the magic value for 1ms.
 	 */
-	outb(CLK_PORT4, 0x30);
-	outb(CLK_PORT1, 0xff);
-	outb(CLK_PORT1, 0xff);
+	pio_write_8(CLK_PORT4, 0x30);
+	pio_write_8(CLK_PORT1, 0xff);
+	pio_write_8(CLK_PORT1, 0xff);
 
 	do {
 		/* will read both status and count */
-		outb(CLK_PORT4, 0xc2);
-		not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1);
-		t1 = inb(CLK_PORT1);
-		t1 |= inb(CLK_PORT1) << 8;
+		pio_write_8(CLK_PORT4, 0xc2);
+		not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1);
+		t1 = pio_read_8(CLK_PORT1);
+		t1 |= pio_read_8(CLK_PORT1) << 8;
 	} while (not_ok);
 
 	asm_delay_loop(LOOPS);
 
-	outb(CLK_PORT4, 0xd2);
-	t2 = inb(CLK_PORT1);
-	t2 |= inb(CLK_PORT1) << 8;
+	pio_write_8(CLK_PORT4, 0xd2);
+	t2 = pio_read_8(CLK_PORT1);
+	t2 |= pio_read_8(CLK_PORT1) << 8;
 
 	/*
 	 * We want to determine the overhead of the calibrating mechanism.
 	 */
-	outb(CLK_PORT4, 0xd2);
-	o1 = inb(CLK_PORT1);
-	o1 |= inb(CLK_PORT1) << 8;
+	pio_write_8(CLK_PORT4, 0xd2);
+	o1 = pio_read_8(CLK_PORT1);
+	o1 |= pio_read_8(CLK_PORT1) << 8;
 
 	asm_fake_loop(LOOPS);
 
-	outb(CLK_PORT4, 0xd2);
-	o2 = inb(CLK_PORT1);
-	o2 |= inb(CLK_PORT1) << 8;
+	pio_write_8(CLK_PORT4, 0xd2);
+	o2 = pio_read_8(CLK_PORT1);
+	o2 |= pio_read_8(CLK_PORT1) << 8;
 
 	CPU->delay_loop_const =
Index: kernel/arch/ia32/src/drivers/i8259.c
===================================================================
--- kernel/arch/ia32/src/drivers/i8259.c	(revision 687c3cd5921e1d47b5311bdcf4dfbc5f55ee093b)
+++ kernel/arch/ia32/src/drivers/i8259.c	(revision 76dd25b7f1290f21230e4d3c41919e84f05bb9d8)
@@ -50,26 +50,26 @@
 {
 	/* ICW1: this is ICW1, ICW4 to follow */
-	outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
+	pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
 
 	/* ICW2: IRQ 0 maps to INT IRQBASE */
-	outb(PIC_PIC0PORT2, IVT_IRQBASE);
+	pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE);
 
 	/* ICW3: pic1 using IRQ IRQ_PIC1 */
-	outb(PIC_PIC0PORT2, 1 << IRQ_PIC1);
+	pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1);
 
 	/* ICW4: i8086 mode */
-	outb(PIC_PIC0PORT2, 1);
+	pio_write_8(PIC_PIC0PORT2, 1);
 
 	/* ICW1: ICW1, ICW4 to follow */
-	outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
+	pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
 
 	/* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
-	outb(PIC_PIC1PORT2, IVT_IRQBASE + 8);
+	pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8);
 
 	/* ICW3: pic1 is known as IRQ_PIC1 */
-	outb(PIC_PIC1PORT2, IRQ_PIC1);
+	pio_write_8(PIC_PIC1PORT2, IRQ_PIC1);
 
 	/* ICW4: i8086 mode */
-	outb(PIC_PIC1PORT2, 1);
+	pio_write_8(PIC_PIC1PORT2, 1);
 
 	/*
@@ -95,10 +95,10 @@
 
 	if (irqmask & 0xff) {
-		x = inb(PIC_PIC0PORT2);
-		outb(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
+		x = pio_read_8(PIC_PIC0PORT2);
+		pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
 	}
 	if (irqmask >> 8) {
-		x = inb(PIC_PIC1PORT2);
-		outb(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
+		x = pio_read_8(PIC_PIC1PORT2);
+		pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
 	}
 }
@@ -109,10 +109,10 @@
 
 	if (irqmask & 0xff) {
-		x = inb(PIC_PIC0PORT2);
-		outb(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
+		x = pio_read_8(PIC_PIC0PORT2);
+		pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
 	}
 	if (irqmask >> 8) {
-		x = inb(PIC_PIC1PORT2);
-		outb(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
+		x = pio_read_8(PIC_PIC1PORT2);
+		pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
 	}
 }
@@ -120,6 +120,6 @@
 void pic_eoi(void)
 {
-	outb(0x20, 0x20);
-	outb(0xa0, 0x20);
+	pio_write_8(0x20, 0x20);
+	pio_write_8(0xa0, 0x20);
 }
 
Index: kernel/arch/ia32/src/smp/smp.c
===================================================================
--- kernel/arch/ia32/src/smp/smp.c	(revision 687c3cd5921e1d47b5311bdcf4dfbc5f55ee093b)
+++ kernel/arch/ia32/src/smp/smp.c	(revision 76dd25b7f1290f21230e4d3c41919e84f05bb9d8)
@@ -123,6 +123,6 @@
 	 * BIOS will not do the POST after the INIT signal.
 	 */
-	outb(0x70, 0xf);
-	outb(0x71, 0xa);
+	pio_write_8(0x70, 0xf);
+	pio_write_8(0x71, 0xa);
 
 	pic_disable_irqs(0xffff);