Index: arch/ppc32/include/asm.h
===================================================================
--- arch/ppc32/include/asm.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/asm.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -41,8 +41,8 @@
  */
 static inline ipl_t interrupts_enable(void) {
-	ipl_t v;
+	ipl_t v = 0;
 	ipl_t tmp;
 	
-	__asm__ volatile (
+	asm volatile (
 		"mfmsr %0\n"
 		"mfmsr %1\n"
@@ -65,5 +65,5 @@
 	ipl_t tmp;
 	
-	__asm__ volatile (
+	asm volatile (
 		"mfmsr %0\n"
 		"mfmsr %1\n"
@@ -84,5 +84,5 @@
 	ipl_t tmp;
 	
-	__asm__ volatile (
+	asm volatile (
 		"mfmsr %1\n"
 		"rlwimi  %0, %1, 0, 17, 15\n"
@@ -104,5 +104,6 @@
 static inline ipl_t interrupts_read(void) {
 	ipl_t v;
-	__asm__ volatile (
+	
+	asm volatile (
 		"mfmsr %0\n"
 		: "=r" (v)
@@ -121,6 +122,9 @@
 	__address v;
 	
-	__asm__ volatile ("and %0, %%sp, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
-	
+	asm volatile (
+		"and %0, %%sp, %1\n"
+		: "=r" (v)
+		: "r" (~(STACK_SIZE - 1))
+	);
 	return v;
 }
Index: arch/ppc32/include/asm/regname.h
===================================================================
--- arch/ppc32/include/asm/regname.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/asm/regname.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -195,4 +195,6 @@
 #define msr_ir	(1 << 4)
 #define msr_dr	(1 << 5)
+#define msr_pr	(1 << 14)
+#define msr_ee	(1 << 15)
 
 /* HID0 bits */
Index: arch/ppc32/include/atomic.h
===================================================================
--- arch/ppc32/include/atomic.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/atomic.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -34,5 +34,5 @@
 	long tmp;
 
-	asm __volatile__ (
+	asm volatile (
 		"1:\n"
 		"lwarx %0, 0, %2\n"
@@ -42,5 +42,6 @@
 		: "=&r" (tmp), "=m" (val->count)
 		: "r" (&val->count), "m" (val->count)
-		: "cc");
+		: "cc"
+	);
 }
 
@@ -49,5 +50,5 @@
 	long tmp;
 
-	asm __volatile__(
+	asm volatile (
 		"1:\n"
 		"lwarx %0, 0, %2\n"
@@ -57,5 +58,6 @@
 		: "=&r" (tmp), "=m" (val->count)
 		: "r" (&val->count), "m" (val->count)
-		: "cc");
+		: "cc"
+	);
 }
 
Index: arch/ppc32/include/barrier.h
===================================================================
--- arch/ppc32/include/barrier.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/barrier.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -30,10 +30,10 @@
 #define __ppc32_BARRIER_H__
 
-#define CS_ENTER_BARRIER()	__asm__ volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()	asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()	asm volatile ("" ::: "memory")
 
-#define memory_barrier() __asm__ volatile ("sync" ::: "memory")
-#define read_barrier() __asm__ volatile ("sync" ::: "memory")
-#define write_barrier() __asm__ volatile ("eieio" ::: "memory")
+#define memory_barrier() asm volatile ("sync" ::: "memory")
+#define read_barrier() asm volatile ("sync" ::: "memory")
+#define write_barrier() asm volatile ("eieio" ::: "memory")
 
 #endif
Index: arch/ppc32/include/byteorder.h
===================================================================
--- arch/ppc32/include/byteorder.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/byteorder.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -52,7 +52,11 @@
 	__address v;
 	
-	__asm__ volatile ("lwbrx %0, %1, %2\n" : "=r" (v) : "i" (0) , "r" (&n));
-	
+	asm volatile (
+		"lwbrx %0, %1, %2\n"
+		: "=r" (v)
+		: "i" (0), "r" (&n)
+	);
 	return v;
 }
+
 #endif
Index: arch/ppc32/include/cpuid.h
===================================================================
--- arch/ppc32/include/cpuid.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/cpuid.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -39,6 +39,6 @@
 static inline void cpu_version(struct cpu_info *info)
 {
-	__asm__ volatile (
-		"mfspr %0, 287\n"
+	asm volatile (
+		"mfpvr %0\n"
 		: "=r" (*info)
 	);
Index: arch/ppc32/include/exception.h
===================================================================
--- arch/ppc32/include/exception.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/exception.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -48,5 +48,4 @@
 	__u32 r10;
 	__u32 r11;
-	__u32 r12;
 	__u32 r13;
 	__u32 r14;
Index: arch/ppc32/include/interrupt.h
===================================================================
--- arch/ppc32/include/interrupt.h	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/include/interrupt.h	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -30,6 +30,5 @@
 #define __ppc32_INTERRUPT_H__
 
-#define IRQ_COUNT	1	/* TODO */
-
+#define IRQ_COUNT	1
 #define IVT_ITEMS   15
 #define INT_OFFSET  0
Index: arch/ppc32/src/asm.S
===================================================================
--- arch/ppc32/src/asm.S	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/src/asm.S	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -40,5 +40,7 @@
 	# r3 = uspace_uarg
 	# r4 = stack
-	# r5 = entry	
+	# r5 = entry
+	
+	# disable interrupts
 
 	mfmsr r31
@@ -52,6 +54,6 @@
 	# set problem state, enable interrupts
 	
-	ori r31, r31, 1 << 14
-	ori r31, r31, 1 << 15
+	ori r31, r31, msr_pr
+	ori r31, r31, msr_ee
 	mtsrr1 r31
 	
@@ -65,22 +67,4 @@
 
 iret:
-	lwz r3, 144(sp)
-	mtxer r3
-	
-	lwz r3, 140(sp)
-	mtctr r3
-	
-	lwz r3, 136(sp)
-	mtcr r3
-	
-	lwz r3, 132(sp)
-	mtlr r3
-	
-	lwz r3, 128(sp)
-	mtspr srr1, r3
-	
-	lwz r3, 124(sp)
-	mtspr srr0, r3
-	
 	lwz r0, 0(sp)
 	lwz r2, 4(sp)
@@ -94,26 +78,44 @@
 	lwz r10, 36(sp)
 	lwz r11, 40(sp)
-	lwz r12, 44(sp)
-	lwz r13, 48(sp)
-	lwz r14, 52(sp)
-	lwz r15, 56(sp)
-	lwz r16, 60(sp)
-	lwz r17, 64(sp)
-	lwz r18, 68(sp)
-	lwz r19, 72(sp)
-	lwz r20, 76(sp)
-	lwz r21, 80(sp)
-	lwz r22, 84(sp)
-	lwz r23, 88(sp)
-	lwz r24, 92(sp)
-	lwz r25, 96(sp)
-	lwz r26, 100(sp)
-	lwz r27, 104(sp)
-	lwz r28, 108(sp)
-	lwz r29, 112(sp)
-	lwz r30, 116(sp)
-	lwz r31, 120(sp)
-	
-	mfspr sp, sprg1
+	lwz r13, 44(sp)
+	lwz r14, 48(sp)
+	lwz r15, 52(sp)
+	lwz r16, 56(sp)
+	lwz r17, 60(sp)
+	lwz r18, 64(sp)
+	lwz r19, 68(sp)
+	lwz r20, 72(sp)
+	lwz r21, 76(sp)
+	lwz r22, 80(sp)
+	lwz r23, 84(sp)
+	lwz r24, 88(sp)
+	lwz r25, 92(sp)
+	lwz r26, 96(sp)
+	lwz r27, 100(sp)
+	lwz r28, 104(sp)
+	lwz r29, 108(sp)
+	lwz r30, 112(sp)
+	lwz r31, 116(sp)
+	
+	lwz r12, 120(sp)
+	mtsrr0 r12
+	
+	lwz r12, 124(sp)
+	mtsrr1 r12
+	
+	lwz r12, 128(sp)
+	mtlr r12
+	
+	lwz r12, 132(sp)
+	mtcr r12
+	
+	lwz r12, 136(sp)
+	mtctr r12
+	
+	lwz r12, 140(sp)
+	mtxer r12
+
+	mfsprg1 sp
+	mfsprg2 r12
 	
 	rfi
Index: arch/ppc32/src/boot/boot.S
===================================================================
--- arch/ppc32/src/boot/boot.S	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/src/boot/boot.S	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -35,16 +35,19 @@
 kernel_image_start:
 
-	# load temporary stack
+	# load temporal kernel stack
 	
-	lis sp, end_stack@ha
-	addi sp, sp, end_stack@l
+	lis sp, kernel_stack@ha
+	addi sp, sp, kernel_stack@l
+	
+	# set kernel stack for interrupt handling
+	
+	mr r31, sp
+	subis r31, r31, 0x8000
+	mtsprg0 r31
 	
 	# r3 contains physical address of bootinfo_t
 	# r4 contains size of bootinfo_t
 	
-	lis r31, 0x80000000@ha
-	addi r31, r31, 0x80000000@l
-	
-	add r3, r3, r31
+	addis r3, r3, 0x8000
 
 	lis r31, bootinfo@ha
@@ -73,4 +76,6 @@
 .section K_DATA_START, "aw", @progbits
 
+.align 12
+kernel_stack_bottom:
 	.space TEMP_STACK_SIZE
-end_stack:
+kernel_stack:
Index: arch/ppc32/src/exception.S
===================================================================
--- arch/ppc32/src/exception.S	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/src/exception.S	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -33,9 +33,33 @@
 
 .macro CONTEXT_STORE
-	mtspr sprg1, sp
-	
-	subis sp, sp, 0x8000
-	
-	subi sp, sp, 144
+	
+	# save SP in SPRG1
+	# save R12 in SPRG2, backup CR in R12
+
+	mtsprg1 sp
+	mtsprg2 r12
+	mfcr r12
+	
+	# check whether SP is in kernel
+	
+	andis. sp, sp, 0x8000
+	bne 1f
+	
+		# stack is in user-space
+		
+		mfsprg0 sp
+	
+	b 2f
+	
+	1:
+	
+		# stack is in kernel
+		
+		mfsprg1 sp
+		subis sp, sp, 0x8000
+	
+	2:
+	
+	subi sp, sp, 140
 	stw r0, 0(sp)
 	stw r2, 4(sp)
@@ -49,42 +73,40 @@
 	stw r10, 36(sp)
 	stw r11, 40(sp)
-	stw r12, 44(sp)
-	stw r13, 48(sp)
-	stw r14, 52(sp)
-	stw r15, 56(sp)
-	stw r16, 60(sp)
-	stw r17, 64(sp)
-	stw r18, 68(sp)
-	stw r19, 72(sp)
-	stw r20, 76(sp)
-	stw r21, 80(sp)
-	stw r22, 84(sp)
-	stw r23, 88(sp)
-	stw r24, 92(sp)
-	stw r25, 96(sp)
-	stw r26, 100(sp)
-	stw r27, 104(sp)
-	stw r28, 108(sp)
-	stw r29, 112(sp)
-	stw r30, 116(sp)
-	stw r31, 120(sp)
-	
-	mfspr r3, srr0
+	stw r13, 44(sp)
+	stw r14, 48(sp)
+	stw r15, 52(sp)
+	stw r16, 56(sp)
+	stw r17, 60(sp)
+	stw r18, 64(sp)
+	stw r19, 68(sp)
+	stw r20, 72(sp)
+	stw r21, 76(sp)
+	stw r22, 80(sp)
+	stw r23, 84(sp)
+	stw r24, 88(sp)
+	stw r25, 92(sp)
+	stw r26, 96(sp)
+	stw r27, 100(sp)
+	stw r28, 104(sp)
+	stw r29, 108(sp)
+	stw r30, 112(sp)
+	stw r31, 116(sp)
+	
+	mfsrr0 r3
+	stw r3, 120(sp)
+	
+	mfsrr1 r3
 	stw r3, 124(sp)
 	
-	mfspr r3, srr1
+	mflr r3
 	stw r3, 128(sp)
 	
-	mflr r3
-	stw r3, 132(sp)
-	
-	mfcr r3
+	stw r12, 132(sp)
+	
+	mfctr r3
 	stw r3, 136(sp)
 	
-	mfctr r3
+	mfxer r3
 	stw r3, 140(sp)
-	
-	mfxer r3
-	stw r3, 144(sp)
 .endm
 
@@ -103,12 +125,12 @@
 exc_data_storage:
 	CONTEXT_STORE
-
+	
 	lis r3, pht_refill@ha
 	addi r3, r3, pht_refill@l
-	mtspr srr0, r3
+	mtsrr0 r3
 	
 	mfmsr r3
 	ori r3, r3, (msr_ir | msr_dr)@l
-	mtspr srr1, r3
+	mtsrr1 r3
 	
 	lis r3, iret@ha
@@ -117,4 +139,5 @@
 	
 	addis sp, sp, 0x8000
+	mr r3, sp
 	rfi
 
@@ -122,10 +145,21 @@
 .global exc_instruction_storage
 exc_instruction_storage:
-	b exc_instruction_storage
-
-.org 0x480
-.global exc_instruction_segment
-exc_instruction_segment:
-	b exc_instruction_segment
+	CONTEXT_STORE
+	
+	lis r3, pht_refill@ha
+	addi r3, r3, pht_refill@l
+	mtsrr0 r3
+	
+	mfmsr r3
+	ori r3, r3, (msr_ir | msr_dr)@l
+	mtsrr1 r3
+	
+	lis r3, iret@ha
+	addi r3, r3, iret@l
+	mtlr r3
+	
+	addis sp, sp, 0x8000
+	mr r3, sp
+	rfi
 
 .org 0x500
@@ -156,9 +190,9 @@
 	lis r3, exc_dispatch@ha
 	addi r3, r3, exc_dispatch@l
-	mtspr srr0, r3
+	mtsrr0 r3
 	
 	mfmsr r3
 	ori r3, r3, (msr_ir | msr_dr)@l
-	mtspr srr1, r3
+	mtsrr1 r3
 	
 	lis r3, iret@ha
@@ -168,4 +202,5 @@
 	addis sp, sp, 0x8000
 	li r3, 10
+	mr r4, sp
 	rfi
 
Index: arch/ppc32/src/interrupt.c
===================================================================
--- arch/ppc32/src/interrupt.c	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/src/interrupt.c	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -32,6 +32,6 @@
 #include <arch.h>
 #include <time/clock.h>
-#include <print.h>
 #include <ipc/sysipc.h>
+
 
 void start_decrementer(void)
Index: arch/ppc32/src/proc/scheduler.c
===================================================================
--- arch/ppc32/src/proc/scheduler.c	(revision 0f27b4c9cefc753c19b0596bdf4186910d5c54d9)
+++ arch/ppc32/src/proc/scheduler.c	(revision 762a824d7d738807864445bcf60c992a391a4472)
@@ -28,10 +28,8 @@
 
 #include <arch/mm/page.h>
+#include <arch/boot/boot.h>
 #include <proc/scheduler.h>
 #include <proc/thread.h>
 #include <arch.h>
-
-__address supervisor_sp;
-__address supervisor_sp_physical;
 
 /** Perform ppc32 specific tasks needed before the new task is run. */
@@ -43,6 +41,9 @@
 void before_thread_runs_arch(void)
 {
-	supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA];
-	supervisor_sp_physical = KA2PA(supervisor_sp_physical);
+	asm volatile (
+		"mtsprg0 %0\n"
+		:
+		: "r" (KA2PA(&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]))
+	);
 }
 
