Index: arch/sparc64/include/asm.h
===================================================================
--- arch/sparc64/include/asm.h	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ arch/sparc64/include/asm.h	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -30,6 +30,31 @@
 #define __sparc64_ASM_H__
 
+#include <typedefs.h>
 #include <arch/types.h>
+#include <arch/register.h>
 #include <config.h>
+
+/** Read Processor State register.
+ *
+ * @return Value of PSTATE register.
+ */
+static inline __u64 pstate_read(void)
+{
+	__u64 v;
+	
+	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
+	
+	return v;
+}
+
+/** Write Processor State register.
+ *
+ * @param New value of PSTATE register.
+ */
+static inline void pstate_write(__u64 v)
+{
+	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
+}
+
 
 /** Enable interrupts.
@@ -41,4 +66,13 @@
  */
 static inline ipl_t interrupts_enable(void) {
+	pstate_reg_t pstate;
+	__u64 value;
+	
+	value = pstate_read();
+	pstate.value = value;
+	pstate.ie = true;
+	pstate_write(pstate.value);
+	
+	return (ipl_t) value;
 }
 
@@ -51,4 +85,13 @@
  */
 static inline ipl_t interrupts_disable(void) {
+	pstate_reg_t pstate;
+	__u64 value;
+	
+	value = pstate_read();
+	pstate.value = value;
+	pstate.ie = false;
+	pstate_write(pstate.value);
+	
+	return (ipl_t) value;
 }
 
@@ -60,4 +103,9 @@
  */
 static inline void interrupts_restore(ipl_t ipl) {
+	pstate_reg_t pstate;
+	
+	pstate.value = pstate_read();
+	pstate.ie = ((pstate_reg_t) ipl).ie;
+	pstate_write(pstate.value);
 }
 
@@ -69,4 +117,5 @@
  */
 static inline ipl_t interrupts_read(void) {
+	return (ipl_t) pstate_read();
 }
 
@@ -81,5 +130,5 @@
 	__address v;
 	
-	__asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+	__asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
 	
 	return v;
Index: arch/sparc64/include/context.h
===================================================================
--- arch/sparc64/include/context.h	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ arch/sparc64/include/context.h	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -67,5 +67,6 @@
 	__address sp;		/* %o6 */
 	__address pc;		/* %o7 */
-	__address fp;
+	__address fp;		/* %i6 */
+	__address i7;
 	ipl_t ipl;
 };
Index: arch/sparc64/include/context_offset.h
===================================================================
--- arch/sparc64/include/context_offset.h	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ arch/sparc64/include/context_offset.h	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -9,2 +9,3 @@
 #define OFFSET_PC  0x30
 #define OFFSET_FP  0x38
+#define OFFSET_I7  0x40
Index: arch/sparc64/include/register.h
===================================================================
--- arch/sparc64/include/register.h	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ arch/sparc64/include/register.h	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -47,3 +47,23 @@
 typedef union ver_reg ver_reg_t;
 
+/** Processor State Register. */
+union pstate_reg {
+	__u64 value;
+	struct {
+		__u64 : 52;
+		unsigned ig : 1;	/**< Interrupt Globals. */
+		unsigned mg : 1;	/**< MMU Globals. */
+		unsigned cle : 1;	/**< Current Little Endian. */
+		unsigned tle : 1;	/**< Trap Little Endian. */
+		unsigned mm : 2;	/**< Memory Model. */
+		unsigned red : 1;	/**< RED state. */
+		unsigned pef : 1;	/**< Enable floating-point. */
+		unsigned am : 1;	/**< 32-bit Address Mask. */
+		unsigned priv : 1;	/**< Privileged Mode. */
+		unsigned ie : 1;	/**< Interrupt Enable. */
+		unsigned ag : 1;	/**< Alternate Globals*/
+	} __attribute__ ((packed));
+};
+typedef union pstate_reg pstate_reg_t;
+
 #endif
Index: arch/sparc64/src/context.S
===================================================================
--- arch/sparc64/src/context.S	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ arch/sparc64/src/context.S	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -52,4 +52,5 @@
 	stx %sp, [\r + OFFSET_SP]
 	stx %fp, [\r + OFFSET_FP]
+	stx %i7, [\r + OFFSET_I7]
 .endm
 
@@ -63,4 +64,5 @@
 	ldx [\r + OFFSET_SP], %sp
 	ldx [\r + OFFSET_FP], %fp
+	ldx [\r + OFFSET_I7], %i7
 .endm
 
Index: arch/sparc64/src/dummy.s
===================================================================
--- arch/sparc64/src/dummy.s	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ arch/sparc64/src/dummy.s	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -59,7 +59,5 @@
 userspace:
 
-
 dummy:
-0:
 	retl
 	nop
Index: generic/include/debug.h
===================================================================
--- generic/include/debug.h	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ generic/include/debug.h	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -51,5 +51,5 @@
  */
 #ifdef CONFIG_DEBUG
-#	define ASSERT(expr) if (!(expr)) { panic("assertion failed (%s)", #expr); }
+#	define ASSERT(expr) if (!(expr)) { panic("assertion failed (%s), caller=%P\n", #expr, CALLER); }
 #else
 #	define ASSERT(expr)
Index: generic/src/proc/scheduler.c
===================================================================
--- generic/src/proc/scheduler.c	(revision 031e26427bf76c26ff85a0d574c174809efaae1c)
+++ generic/src/proc/scheduler.c	(revision 75e1db00d0ee9a3395d39a41f301594454557f36)
@@ -295,5 +295,6 @@
 
 			spinlock_lock(&CPU->lock);
-			if(CPU->fpu_owner==THREAD) CPU->fpu_owner=NULL;
+			if(CPU->fpu_owner==THREAD)
+				CPU->fpu_owner=NULL;
 			spinlock_unlock(&CPU->lock);