Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/Makefile.inc (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -33,5 +33,5 @@ ATSIGN = % -GCC_CFLAGS += -march=armv4 -fno-omit-frame-pointer -mapcs-frame +GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access BITS = 32 @@ -74,4 +74,8 @@ endif +ifeq ($(MACHINE),beagleboardxm) + ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c +endif + ifeq ($(CONFIG_PL050),y) ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c Index: kernel/arch/arm32/_link.ld.in =================================================================== --- kernel/arch/arm32/_link.ld.in (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/_link.ld.in (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -9,4 +9,6 @@ #ifdef MACHINE_gta02 #define KERNEL_LOAD_ADDRESS 0xb0a08000 +#elif defined MACHINE_beagleboardxm +#define KERNEL_LOAD_ADDRESS 0x80a00000 #else #define KERNEL_LOAD_ADDRESS 0x80a00000 Index: kernel/arch/arm32/include/asm.h =================================================================== --- kernel/arch/arm32/include/asm.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/asm.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -43,7 +43,17 @@ #include -/** No such instruction on ARM to sleep CPU. */ +/** No such instruction on old ARM to sleep CPU. + * + * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi). + * ARM920T has custom coprocessor action to do the same. See ARM920T Technical + * Reference Manual ch 4.9 p. 4-23 (103 in the PDF) + */ NO_TRACE static inline void cpu_sleep(void) { +#ifdef PROCESSOR_armv7_a + asm volatile ( "wfe" :: ); +#elif defined(MACHINE_gta02) + asm volatile ( "mcr p15,0,R0,c7,c0,4" :: ); +#endif } Index: kernel/arch/arm32/include/barrier.h =================================================================== --- kernel/arch/arm32/include/barrier.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/barrier.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -47,6 +47,24 @@ #define write_barrier() asm volatile ("" ::: "memory") -#define smc_coherence(a) -#define smc_coherence_block(a, l) +/* + * There are multiple ways ICache can be implemented on ARM machines. Namely + * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference + * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum + * compatibility across processors, ARM recommends that operating systems target + * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, + * and do not assume the presence of the IVIPT extension. Software that relies + * on the IVIPT extension might fail in an unpredictable way on an ARMv7 + * implementation that does not include the IVIPT extension." (7.2.6 p. 245). + * Only PIPT invalidates cache for all VA aliases if one block is invalidated. + * + * @note: Supporting ASID and VMID tagged VIVT may need to add ICache + * maintenance to other places than just smc. + */ + +/* Available on both all supported arms, + * invalidates entire ICache so the written value does not matter. */ +#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0") +#define smc_coherence_block(a, l) smc_coherence(a) + #endif Index: kernel/arch/arm32/include/cpu.h =================================================================== --- kernel/arch/arm32/include/cpu.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/cpu.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -41,5 +41,5 @@ -/** Struct representing ARM CPU identifiaction. */ +/** Struct representing ARM CPU identification. */ typedef struct { /** Implementator (vendor) number. */ Index: kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h =================================================================== --- kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) +++ kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm beagleboardxm + * @brief BeagleBoard-xM platform. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief BeagleBoard platform driver. + */ + +#ifndef KERN_arm32_beagleboardxm_H_ +#define KERN_arm32_beagleboardxm_H_ + +#include + +extern struct arm_machine_ops bbxm_machine_ops; + +#endif + +/** @} + */ + Index: kernel/arch/arm32/include/machine_func.h =================================================================== --- kernel/arch/arm32/include/machine_func.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/machine_func.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -108,4 +108,6 @@ extern size_t machine_get_irq_count(void); +extern const char * machine_get_platform_name(void); + #endif Index: kernel/arch/arm32/include/mm/frame.h =================================================================== --- kernel/arch/arm32/include/mm/frame.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/mm/frame.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -48,4 +48,6 @@ #ifdef MACHINE_gta02 #define BOOT_PAGE_TABLE_ADDRESS 0x30010000 +#elif defined MACHINE_beagleboardxm +#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 #else #define BOOT_PAGE_TABLE_ADDRESS 0x00008000 @@ -57,4 +59,6 @@ #ifdef MACHINE_gta02 #define PHYSMEM_START_ADDR 0x30008000 +#elif defined MACHINE_beagleboardxm +#define PHYSMEM_START_ADDR 0x80000000 #else #define PHYSMEM_START_ADDR 0x00000000 Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/mm/page.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -46,4 +46,13 @@ #define PAGE_SIZE FRAME_SIZE +#ifdef MACHINE_beagleboardxm +#ifndef __ASM__ +# define KA2PA(x) ((uintptr_t) (x)) +# define PA2KA(x) ((uintptr_t) (x)) +#else +# define KA2PA(x) (x) +# define PA2KA(x) (x) +#endif +#else #ifndef __ASM__ # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) @@ -53,57 +62,58 @@ # define PA2KA(x) ((x) + 0x80000000) #endif +#endif /* Number of entries in each level. */ -#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ -#define PTL1_ENTRIES_ARCH 0 -#define PTL2_ENTRIES_ARCH 0 +#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 /* coarse page tables used (256 * 4 = 1KB per page) */ -#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ +#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH FOUR_FRAMES -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_SIZE_ARCH FOUR_FRAMES +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME /* Macros calculating indices into page tables for each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) /* Get PTE address accessors for each level. */ #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ - ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) + ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ - (ptl1) + (ptl1) #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ - (ptl2) + (ptl2) #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ - ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) + ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) /* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) \ - (set_ptl0_addr((pte_t *) (ptl0))) + (set_ptl0_addr((pte_t *) (ptl0))) #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ - (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) + (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ - (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) + (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) /* Get PTE flags accessors for each level. */ #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ - get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) + get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ - PAGE_PRESENT + PAGE_PRESENT #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ - PAGE_PRESENT + PAGE_PRESENT #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ - get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) + get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) /* Set PTE flags accessors for each level. */ #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ - set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) + set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) @@ -119,221 +129,11 @@ set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) -/* Macros for querying the last-level PTE entries. */ -#define PTE_VALID_ARCH(pte) \ - (*((uint32_t *) (pte)) != 0) -#define PTE_PRESENT_ARCH(pte) \ - (((pte_t *) (pte))->l0.descriptor_type != 0) -#define PTE_GET_FRAME_ARCH(pte) \ - (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(pte) \ - (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) -#define PTE_EXECUTABLE_ARCH(pte) \ - 1 - -#ifndef __ASM__ - -/** Level 0 page table entry. */ -typedef struct { - /* 0b01 for coarse tables, see below for details */ - unsigned descriptor_type : 2; - unsigned impl_specific : 3; - unsigned domain : 4; - unsigned should_be_zero : 1; - - /* Pointer to the coarse 2nd level page table (holding entries for small - * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page - * tables that may hold even tiny pages (1KB) but they are bigger (4KB - * per table in comparison with 1KB per the coarse table) - */ - unsigned coarse_table_addr : 22; -} ATTRIBUTE_PACKED pte_level0_t; - -/** Level 1 page table entry (small (4KB) pages used). */ -typedef struct { - - /* 0b10 for small pages */ - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; - - /* access permissions for each of 4 subparts of a page - * (for each 1KB when small pages used */ - unsigned access_permission_0 : 2; - unsigned access_permission_1 : 2; - unsigned access_permission_2 : 2; - unsigned access_permission_3 : 2; - unsigned frame_base_addr : 20; -} ATTRIBUTE_PACKED pte_level1_t; - -typedef union { - pte_level0_t l0; - pte_level1_t l1; -} pte_t; - -/* Level 1 page tables access permissions */ - -/** User mode: no access, privileged mode: no access. */ -#define PTE_AP_USER_NO_KERNEL_NO 0 - -/** User mode: no access, privileged mode: read/write. */ -#define PTE_AP_USER_NO_KERNEL_RW 1 - -/** User mode: read only, privileged mode: read/write. */ -#define PTE_AP_USER_RO_KERNEL_RW 2 - -/** User mode: read/write, privileged mode: read/write. */ -#define PTE_AP_USER_RW_KERNEL_RW 3 - - -/* pte_level0_t and pte_level1_t descriptor_type flags */ - -/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_NOT_PRESENT 0 - -/** pte_level0_t coarse page table flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_COARSE_TABLE 1 - -/** pte_level1_t small page table flag (used in descriptor type). */ -#define PTE_DESCRIPTOR_SMALL_PAGE 2 - - -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} - - -/** Returns level 0 page table entry flags. - * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - - return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); -} - -/** Returns level 1 page table entry flags. - * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - int dt = p->descriptor_type; - int ap = p->access_permission_0; - - return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | - ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | - ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | - (p->bufferable << PAGE_CACHEABLE); -} - -/** Sets flags of level 0 page table entry. - * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - * - */ -NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) -{ - pte_level0_t *p = &pt[i].l0; - - if (flags & PAGE_NOT_PRESENT) { - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - /* - * Ensures that the entry will be recognized as valid when - * PTE_VALID_ARCH applied. - */ - p->should_be_zero = 1; - } else { - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; - p->should_be_zero = 0; - } -} - -NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - - p->should_be_zero = 0; - write_barrier(); - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; -} - -/** Sets flags of level 1 page table entry. - * - * We use same access rights for the whole page. When page - * is not preset we store 1 in acess_rigts_3 so that at least - * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - * - */ -NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) -{ - pte_level1_t *p = &pt[i].l1; - - if (flags & PAGE_NOT_PRESENT) - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - else - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; - - p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - - /* default access permission */ - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_NO_KERNEL_RW; - - if (flags & PAGE_USER) { - if (flags & PAGE_READ) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RO_KERNEL_RW; - } - if (flags & PAGE_WRITE) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RW_KERNEL_RW; - } - } -} - -NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; -} - -extern void page_arch_init(void); - -#endif /* __ASM__ */ +#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a) +#include "page_armv6.h" +#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) +#include "page_armv4.h" +#else +#error "Unsupported architecture" +#endif #endif Index: kernel/arch/arm32/include/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv4.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) +++ kernel/arch/arm32/include/mm/page_armv4.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv4_H_ +#define KERN_arm32_PAGE_armv4_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) +#define PTE_EXECUTABLE_ARCH(pte) \ + 1 + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned impl_specific : 3; + unsigned domain : 4; + unsigned should_be_zero : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + + /* access permissions for each of 4 subparts of a page + * (for each 1KB when small pages used */ + unsigned access_permission_0 : 2; + unsigned access_permission_1 : 2; + unsigned access_permission_2 : 2; + unsigned access_permission_3 : 2; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP_USER_NO_KERNEL_RW 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP_USER_RO_KERNEL_RW 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP_USER_RW_KERNEL_RW 3 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + int dt = p->descriptor_type; + int ap = p->access_permission_0; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | + ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; + + /* default access permission */ + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_NO_KERNEL_RW; + + if (flags & PAGE_USER) { + if (flags & PAGE_READ) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RO_KERNEL_RW; + } + if (flags & PAGE_WRITE) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RW_KERNEL_RW; + } + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv6.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) +++ kernel/arch/arm32/include/mm/page_armv6.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv7_H_ +#define KERN_arm32_PAGE_armv7_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO) +#define PTE_EXECUTABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.descriptor_type != PTE_DESCRIPTOR_SMALL_PAGE_NX) + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned pxn : 1; + unsigned ns : 1; + unsigned should_be_zero_0 : 1; + unsigned domain : 4; + unsigned should_be_zero_1 : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages, 0b11 for NX small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + unsigned access_permission_0 : 2; + unsigned tex : 3; + unsigned access_permission_1 : 1; + unsigned shareable : 1; + unsigned non_global : 1; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP0_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP0_USER_NO_KERNEL_FULL 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP0_USER_LIMITED_KERNEL_FULL 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP0_USER_FULL_KERNEL_FULL 3 + +/** Allow writes */ +#define PTE_AP1_RO 1 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + +/** pte_level1_t small page table flag with NX (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + const pte_level0_t *p = &pt[i].l0; + const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + const pte_level1_t *p = &pt[i].l1; + + const unsigned dt = p->descriptor_type; + const unsigned ap0 = p->access_permission_0; + const unsigned ap1 = p->access_permission_1; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) | + ((ap0 == PTE_AP0_USER_LIMITED_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_FULL_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 != PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_USER_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_FULL_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_NO_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero_0 = 1; + p->should_be_zero_1 = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + p->domain = 0; + p->ns = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + } else { + if (flags & PAGE_EXEC) + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; + } + + /* tex=0 buf=1 and cache=1 => normal memory + * tex=0 buf=1 and cache=0 => shareable device mmio + */ + p->cacheable = (flags & PAGE_CACHEABLE); + p->bufferable = 1; + p->tex = 0; + + /* Shareable is ignored for devices (non-cacheable), + * turn it on for normal memory. */ + p->shareable = 1; + + p->non_global = !(flags & PAGE_GLOBAL); + + /* default access permission: kernel only*/ + p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL; + + if (flags & PAGE_USER) { + p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL; + // TODO Fix kernel to use PAGE_WRITE flag properly and + // apply this for kernel pages as well. + if (!(flags & PAGE_WRITE)) + p->access_permission_1 = PTE_AP1_RO; + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/mm/page_fault.h =================================================================== --- kernel/arch/arm32/include/mm/page_fault.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/mm/page_fault.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -40,18 +40,28 @@ -/** Decribes CP15 "fault status register" (FSR). */ -typedef struct { - unsigned status : 3; - unsigned domain : 4; - unsigned zero : 1; - unsigned should_be_zero : 24; -} ATTRIBUTE_PACKED fault_status_t; - - -/** Help union used for casting integer value into #fault_status_t. */ +/** Decribes CP15 "fault status register" (FSR). + * + * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). + */ typedef union { - fault_status_t fs; - uint32_t dummy; -} fault_status_union_t; + struct { + unsigned status : 4; + unsigned domain : 4; + unsigned zero : 1; + unsigned lpae : 1; /**< Needs LPAE support implemented */ + unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */ + unsigned wr : 1; /**< armv6+ only */ + unsigned ext : 1 ; /**< external abort */ + unsigned cm : 1; /**< Cache maintenance, needs LPAE support */ + unsigned should_be_zero : 18; + } data; + struct { + unsigned status : 4; + unsigned sbz0 : 6; + unsigned fs : 1; + unsigned should_be_zero : 21; + } inst; + uint32_t raw; +} fault_status_t; Index: kernel/arch/arm32/include/regutils.h =================================================================== --- kernel/arch/arm32/include/regutils.h (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/include/regutils.h (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -41,5 +41,27 @@ #define STATUS_REG_MODE_MASK 0x1f -#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) +/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference + * Manual ARMv7-A and ARMv7-R edition, page 1687 */ +#define CP15_R1_MMU_EN (1 << 0) +#define CP15_R1_ALIGN_CHECK_EN (1 << 1) /* Allow alignemnt check */ +#define CP15_R1_CACHE_EN (1 << 2) +#define CP15_R1_CP15_BARRIER_EN (1 << 5) +#define CP15_R1_B_EN (1 << 7) /* ARMv6- only big endian switch */ +#define CP15_R1_SWAP_EN (1 << 10) +#define CP15_R1_BRANCH_PREDICT_EN (1 << 11) +#define CP15_R1_INST_CACHE_EN (1 << 12) +#define CP15_R1_HIGH_VECTORS_EN (1 << 13) +#define CP15_R1_ROUND_ROBIN_EN (1 << 14) +#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17) +#define CP15_R1_WRITE_XN_EN (1 << 19) /* Only if virt. supported */ +#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */ +#define CP15_R1_FAST_IRQ_EN (1 << 21) /* Disbale impl.specific features */ +#define CP15_R1_UNALIGNED_EN (1 << 22) /* Must be 1 on armv7 */ +#define CP15_R1_IRQ_VECTORS_EN (1 << 24) +#define CP15_R1_BIG_ENDIAN_EXC (1 << 25) +#define CP15_R1_NMFI_EN (1 << 27) +#define CP15_R1_TEX_REMAP_EN (1 << 28) +#define CP15_R1_ACCESS_FLAG_EN (1 << 29) +#define CP15_R1_THUMB_EXC_EN (1 << 30) /* ARM Processor Operation Modes */ Index: kernel/arch/arm32/src/arm32.c =================================================================== --- kernel/arch/arm32/src/arm32.c (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/src/arm32.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -49,4 +49,5 @@ #include #include +#include /** Performs arm32-specific initialization before main_bsp() is called. */ @@ -116,4 +117,8 @@ { machine_input_init(); + const char *platform = machine_get_platform_name(); + + sysinfo_set_item_data("platform", NULL, (void *) platform, + str_size(platform)); } Index: kernel/arch/arm32/src/cpu/cpu.c =================================================================== --- kernel/arch/arm32/src/cpu/cpu.c (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/src/cpu/cpu.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -44,14 +44,17 @@ /** Implementators (vendor) names */ static const char *imp_data[] = { - "?", /* IMP_DATA_START_OFFSET */ - "ARM Ltd", /* 0x41 */ - "", /* 0x42 */ - "", /* 0x43 */ - "Digital Equipment Corporation", /* 0x44 */ - "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */ - "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */ - "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */ - "", "", "", "", "", "", /* 0x63 - 0x68 */ - "Intel Corporation" /* 0x69 */ + "?", /* IMP_DATA_START_OFFSET */ + "ARM Limited", /* 0x41 */ + "", "", /* 0x42 - 0x43 */ + "Digital Equipment Corporation", /* 0x44 */ + "", "", "", "", "", "", "", "", /* 0x45 - 0x4c */ + "Motorola, Freescale Semicondutor Inc.", /* 0x4d */ + "", "", "", /* 0x4e - 0x50 */ + "Qualcomm Inc.", /* 0x51 */ + "", "", "", "", /* 0x52 - 0x55 */ + "Marvell Semiconductor", /* 0x56 */ + "", "", "", "", "", "", "", "", "", "", /* 0x57 - 0x60 */ + "", "", "", "", "", "", "", "", /* 0x61 - 0x68 */ + "Intel Corporation" /* 0x69 */ }; @@ -94,11 +97,47 @@ } -/** Does nothing on ARM. */ +/** Enables unaligned access and caching for armv6+ */ void cpu_arch_init(void) { +#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6) + uint32_t control_reg = 0; + asm volatile ( + "mrc p15, 0, %[control_reg], c1, c0" + : [control_reg] "=r" (control_reg) + ); + + /* Turn off tex remap, RAZ ignores writes prior to armv7 */ + control_reg &= ~CP15_R1_TEX_REMAP_EN; + /* Turn off accessed flag, RAZ ignores writes prior to armv7 */ + control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN); + /* Enable unaligned access, RAZ ignores writes prior to armv6 + * switchable on armv6, RAO ignores writes on armv7, + * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition + * L.3.1 (p. 2456) */ + control_reg |= CP15_R1_UNALIGNED_EN; + /* Disable alignment checks, this turns unaligned access to undefined, + * unless U bit is set. */ + control_reg &= ~CP15_R1_ALIGN_CHECK_EN; + /* Enable caching, On arm prior to armv7 there is only one level + * of caches. Data cache is coherent. + * "This means that the behavior of accesses from the same observer to + * different VAs, that are translated to the same PA + * with the same memory attributes, is fully coherent." + * ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition + * B3.11.1 (p. 1383) + * ICache coherency is elaborate on in barrier.h. + * We are safe to turn these on. + */ + control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN; + + asm volatile ( + "mcr p15, 0, %[control_reg], c1, c0" + :: [control_reg] "r" (control_reg) + ); +#endif } /** Retrieves processor identification and stores it to #CPU.arch */ -void cpu_identify(void) +void cpu_identify(void) { arch_cpu_identify(&CPU->arch); @@ -112,11 +151,12 @@ cpu_arch_t * cpu_arch = &m->arch; - if ((cpu_arch->imp_num) > 0 && - (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) { + const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET; + + if (imp_offset < imp_data_length) { vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET]; } - if ((cpu_arch->arch_num) > 0 && - (cpu_arch->arch_num < arch_data_length)) { + // TODO CPUs with arch_num == 0xf use CPUID scheme for identification + if (cpu_arch->arch_num < arch_data_length) { architecture = arch_data[cpu_arch->arch_num]; } Index: kernel/arch/arm32/src/exception.c =================================================================== --- kernel/arch/arm32/src/exception.c (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/src/exception.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -117,9 +117,24 @@ #ifdef HIGH_EXCEPTION_VECTORS -/** Activates use of high exception vectors addresses. */ +/** Activates use of high exception vectors addresses. + * + * "High vectors were introduced into some implementations of ARMv4 and are + * required in ARMv6 implementations. High vectors allow the exception vector + * locations to be moved from their normal address range 0x00000000-0x0000001C + * at the bottom of the 32-bit address space, to an alternative address range + * 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative + * locations are known as the high vectors. + * + * Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are + * supported. When they are, a hardware configuration input selects whether + * the normal vectors or the high vectors are to be used from + * reset." ARM Architecture Reference Manual A2.6.11 (p. 64 in the PDF). + * + * ARM920T (gta02) TRM A2.3.5 (PDF p. 36) and ARM926EJ-S (icp) 2.3.2 (PDF p. 42) + * say that armv4 an armv5 chips that we support implement this. + */ static void high_vectors(void) { - uint32_t control_reg; - + uint32_t control_reg = 0; asm volatile ( "mrc p15, 0, %[control_reg], c1, c0" @@ -128,5 +143,5 @@ /* switch on the high vectors bit */ - control_reg |= CP15_R1_HIGH_VECTORS_BIT; + control_reg |= CP15_R1_HIGH_VECTORS_EN; asm volatile ( @@ -153,4 +168,5 @@ void exception_init(void) { + // TODO check for availability of high vectors for <= armv5 #ifdef HIGH_EXCEPTION_VECTORS high_vectors(); Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c =================================================================== --- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) +++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm + * @{ + */ +/** @file + * @brief BeagleBoard-xM platform driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void bbxm_init(void); +static void bbxm_timer_irq_start(void); +static void bbxm_cpu_halt(void); +static void bbxm_get_memory_extents(uintptr_t *start, size_t *size); +static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate); +static void bbxm_frame_init(void); +static void bbxm_output_init(void); +static void bbxm_input_init(void); +static size_t bbxm_get_irq_count(void); +static const char *bbxm_get_platform_name(void); + +#define BBXM_MEMORY_START 0x80000000 /* physical */ +#define BBXM_MEMORY_SIZE 0x20000000 /* 512 MB */ + +static struct beagleboard { + amdm37x_dispc_regs_t *dispc; + amdm37x_irc_regs_t *irc_addr; + amdm37x_uart_t uart; + amdm37x_gpt_t timer; +} beagleboard; + +struct arm_machine_ops bbxm_machine_ops = { + .machine_init = bbxm_init, + .machine_timer_irq_start = bbxm_timer_irq_start, + .machine_cpu_halt = bbxm_cpu_halt, + .machine_get_memory_extents = bbxm_get_memory_extents, + .machine_irq_exception = bbxm_irq_exception, + .machine_frame_init = bbxm_frame_init, + .machine_output_init = bbxm_output_init, + .machine_input_init = bbxm_input_init, + .machine_get_irq_count = bbxm_get_irq_count, + .machine_get_platform_name = bbxm_get_platform_name +}; + +static irq_ownership_t bb_timer_irq_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void bbxm_setup_fb(unsigned width, unsigned height, unsigned bpp) +{ + const unsigned pixel_bytes = (bpp / 8); + const size_t size = ALIGN_UP(width * height * pixel_bytes, FRAME_SIZE); + const unsigned frames = size / FRAME_SIZE; + unsigned order = 0; + unsigned frame = 1; + while (frame < frames) { + frame *= 2; + ++order; + } + /* prefer highmem as we don't care about virtual mapping. */ + void *buffer = frame_alloc(order, FRAME_LOWMEM); + if (!buffer) { + printf("Failed to allocate framebuffer.\n"); + return; + } + + amdm37x_dispc_setup_fb(beagleboard.dispc, width, height, bpp, + (uintptr_t) buffer); + + fb_properties_t prop = { + .addr = (uintptr_t)buffer, + .offset = 0, + .x = width, + .y = height, + .scan = width * pixel_bytes, + .visual = VISUAL_RGB_5_6_5_LE + }; + switch (bpp) + { + case 8: + prop.visual = VISUAL_INDIRECT_8; break; + case 16: + prop.visual = VISUAL_RGB_5_6_5_LE; break; + case 24: + prop.visual = VISUAL_BGR_8_8_8; break; + case 32: + prop.visual = VISUAL_RGB_8_8_8_0; break; + default: + printf("Invalid framebuffer bit depth: bailing out.\n"); + return; + } + outdev_t *fb_dev = fb_init(&prop); + if (fb_dev) + stdout_wire(fb_dev); + +} + +static void bb_timer_irq_handler(irq_t *irq) +{ + /* + * We are holding a lock which prevents preemption. + * Release the lock, call clock() and reacquire the lock again. + */ + amdm37x_gpt_irq_ack(&beagleboard.timer); + spinlock_unlock(&irq->lock); + clock(); + spinlock_lock(&irq->lock); +} + +static void bbxm_init(void) +{ + /* Initialize interrupt controller */ + beagleboard.irc_addr = + (void *) km_map(AMDM37x_IRC_BASE_ADDRESS, AMDM37x_IRC_SIZE, + PAGE_NOT_CACHEABLE); + ASSERT(beagleboard.irc_addr); + amdm37x_irc_init(beagleboard.irc_addr); + + /* Map display controller */ + beagleboard.dispc = (void*) km_map(AMDM37x_DISPC_BASE_ADDRESS, + AMDM37x_DISPC_SIZE, PAGE_NOT_CACHEABLE); + ASSERT(beagleboard.dispc); + + /* Initialize timer. Use timer1, because it is in WKUP power domain + * (always on) and has special capabilities for precise 1ms ticks */ + amdm37x_gpt_timer_ticks_init(&beagleboard.timer, + AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ); +} + +static void bbxm_timer_irq_start(void) +{ + /* Initialize timer IRQ */ + static irq_t timer_irq; + irq_initialize(&timer_irq); + timer_irq.devno = device_assign_devno(); + timer_irq.inr = AMDM37x_GPT1_IRQ; + timer_irq.claim = bb_timer_irq_claim; + timer_irq.handler = bb_timer_irq_handler; + irq_register(&timer_irq); + + /* Enable timer interrupt */ + amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ); + + /* Start timer here */ + amdm37x_gpt_timer_ticks_start(&beagleboard.timer); +} + +static void bbxm_cpu_halt(void) +{ + while (1); +} + +/** Get extents of available memory. + * + * @param start Place to store memory start address (physical). + * @param size Place to store memory size. + */ +static void bbxm_get_memory_extents(uintptr_t *start, size_t *size) +{ + *start = BBXM_MEMORY_START; + *size = BBXM_MEMORY_SIZE; +} + +static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate) +{ + const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr); + amdm37x_irc_irq_ack(beagleboard.irc_addr); + + irq_t *irq = irq_dispatch_and_lock(inum); + if (irq) { + /* The IRQ handler was found. */ + irq->handler(irq); + spinlock_unlock(&irq->lock); + } else { + /* Spurious interrupt.*/ + printf("cpu%d: spurious interrupt (inum=%d)\n", + CPU->id, inum); + } +} + +static void bbxm_frame_init(void) +{ +} + +static void bbxm_output_init(void) +{ +#ifdef CONFIG_FB + bbxm_setup_fb(CONFIG_BFB_WIDTH, CONFIG_BFB_HEIGHT, CONFIG_BFB_BPP); +#else + (void)bbxm_setup_fb; +#endif + /* UART3 is wired to external RS232 connector */ + const bool ok = amdm37x_uart_init(&beagleboard.uart, + AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE); + if (ok) { + stdout_wire(&beagleboard.uart.outdev); + } +} + +static void bbxm_input_init(void) +{ + srln_instance_t *srln_instance = srln_init(); + if (srln_instance) { + indev_t *sink = stdin_wire(); + indev_t *srln = srln_wire(srln_instance, sink); + amdm37x_uart_input_wire(&beagleboard.uart, srln); + amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ); + } +} + +size_t bbxm_get_irq_count(void) +{ + return AMDM37x_IRC_IRQ_COUNT; +} + +const char *bbxm_get_platform_name(void) +{ + return "beagleboardxm"; +} + +/** + * @} + */ Index: kernel/arch/arm32/src/machine_func.c =================================================================== --- kernel/arch/arm32/src/machine_func.c (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/src/machine_func.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -42,4 +42,5 @@ #include #include +#include /** Pointer to machine_ops structure being used. */ @@ -55,4 +56,6 @@ #elif defined(MACHINE_integratorcp) machine_ops = &icp_machine_ops; +#elif defined(MACHINE_beagleboardxm) + machine_ops = &bbxm_machine_ops; #else #error Machine type not defined. @@ -131,4 +134,10 @@ } +const char * machine_get_platform_name(void) +{ + if (machine_ops->machine_get_platform_name) + return machine_ops->machine_get_platform_name(); + return NULL; +} /** @} */ Index: kernel/arch/arm32/src/mm/page.c =================================================================== --- kernel/arch/arm32/src/mm/page.c (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/src/mm/page.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -52,14 +52,16 @@ void page_arch_init(void) { - int flags = PAGE_CACHEABLE; + int flags = PAGE_CACHEABLE | PAGE_EXEC; page_mapping_operations = &pt_mapping_operations; page_table_lock(AS_KERNEL, true); - uintptr_t cur; - /* Kernel identity mapping */ - for (cur = PHYSMEM_START_ADDR; - cur < min(config.identity_size, config.physmem_end); + //FIXME: We need to consider the possibility that + //identity_base > identity_size and physmem_end. + //This might lead to overflow if identity_size is too big. + for (uintptr_t cur = PHYSMEM_START_ADDR; + cur < min(KA2PA(config.identity_base) + + config.identity_size, config.physmem_end); cur += FRAME_SIZE) page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); Index: kernel/arch/arm32/src/mm/page_fault.c =================================================================== --- kernel/arch/arm32/src/mm/page_fault.c (revision 1dbc43f1c037ded959f69e4b6346df8bf12e2431) +++ kernel/arch/arm32/src/mm/page_fault.c (revision 7462674581270cbc4c5e0b2d1075ebff0d1aec55) @@ -42,27 +42,124 @@ #include -/** Returns value stored in fault status register. + +/** + * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition. + * + * B3.13.3 page B3-1406 (PDF page 1406) + */ +typedef enum { + DFSR_SOURCE_ALIGN = 0x0001, + DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004, + DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c, + DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e, + DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c, + DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e, + DFSR_SOURCE_TRANSLATION_L1 = 0x0005, + DFSR_SOURCE_TRANSLATION_L2 = 0x0007, + DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */ + DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006, + DFSR_SOURCE_DOMAIN_L1 = 0x0009, + DFSR_SOURCE_DOMAIN_L2 = 0x000b, + DFSR_SOURCE_PERMISSION_L1 = 0x000d, + DFSR_SOURCE_PERMISSION_L2 = 0x000f, + DFSR_SOURCE_DEBUG = 0x0002, + DFSR_SOURCE_SYNC_EXTERNAL = 0x0008, + DFSR_SOURCE_TLB_CONFLICT = 0x0400, + DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */ + DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */ + DFSR_SOURCE_SYNC_PARITY = 0x0409, + DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406, + DFSR_SOURCE_ASYNC_PARITY = 0x0408, + DFSR_SOURCE_MASK = 0x0000040f, +} dfsr_source_t; + +static inline const char * dfsr_source_to_str(dfsr_source_t source) +{ + switch (source) { + case DFSR_SOURCE_TRANSLATION_L1: + return "Translation fault L1"; + case DFSR_SOURCE_TRANSLATION_L2: + return "Translation fault L2"; + case DFSR_SOURCE_PERMISSION_L1: + return "Permission fault L1"; + case DFSR_SOURCE_PERMISSION_L2: + return "Permission fault L2"; + case DFSR_SOURCE_ALIGN: + return "Alignment fault"; + case DFSR_SOURCE_CACHE_MAINTENANCE: + return "Instruction cache maintenance fault"; + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1: + return "Synchronous external abort on translation table walk level 1"; + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2: + return "Synchronous external abort on translation table walk level 2"; + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1: + return "Synchronous parity error on translation table walk level 1"; + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2: + return "Synchronous parity error on translation table walk level 2"; + case DFSR_SOURCE_ACCESS_FLAG_L1: + return "Access flag fault L1"; + case DFSR_SOURCE_ACCESS_FLAG_L2: + return "Access flag fault L2"; + case DFSR_SOURCE_DOMAIN_L1: + return "Domain fault L1"; + case DFSR_SOURCE_DOMAIN_L2: + return "Domain flault L2"; + case DFSR_SOURCE_DEBUG: + return "Debug event"; + case DFSR_SOURCE_SYNC_EXTERNAL: + return "Synchronous external abort"; + case DFSR_SOURCE_TLB_CONFLICT: + return "TLB conflict abort"; + case DFSR_SOURCE_LOCKDOWN: + return "Lockdown (Implementation defined)"; + case DFSR_SOURCE_COPROCESSOR: + return "Coprocessor abort (Implementation defined)"; + case DFSR_SOURCE_SYNC_PARITY: + return "Synchronous parity error on memory access"; + case DFSR_SOURCE_ASYNC_EXTERNAL: + return "Asynchronous external abort"; + case DFSR_SOURCE_ASYNC_PARITY: + return "Asynchronous parity error on memory access"; + case DFSR_SOURCE_MASK: + break; + } + return "Unknown data abort"; +} + + +/** Returns value stored in comnbined/data fault status register. * * @return Value stored in CP15 fault status register (FSR). - */ -static inline fault_status_t read_fault_status_register(void) -{ - fault_status_union_t fsu; + * + * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR. + * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of + * the architecture. A write flag (bit[11] of the DFSR) has also been + * introduced." + * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719) + * + * See ch. B4.9.6 for location of data/instruction FSR. + * + */ +static inline fault_status_t read_data_fault_status_register(void) +{ + fault_status_t fsu; - /* fault status is stored in CP15 register 5 */ + /* Combined/Data fault status is stored in CP15 register 5, c0. */ asm volatile ( "mrc p15, 0, %[dummy], c5, c0, 0" - : [dummy] "=r" (fsu.dummy) + : [dummy] "=r" (fsu.raw) ); - return fsu.fs; -} - -/** Returns FAR (fault address register) content. - * - * @return FAR (fault address register) content (address that caused a page + return fsu; +} + +/** Returns DFAR (fault address register) content. + * + * This register is equivalent to FAR on pre armv6 machines. + * + * @return DFAR (fault address register) content (address that caused a page * fault) */ -static inline uintptr_t read_fault_address_register(void) +static inline uintptr_t read_data_fault_address_register(void) { uintptr_t ret; @@ -77,4 +174,5 @@ } +#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) /** Decides whether read or write into memory is requested. * @@ -97,5 +195,5 @@ panic("page_fault - instruction does not access memory " "(instr_code: %#0" PRIx32 ", badvaddr:%p).", - instr_union.pc, (void *) badvaddr); + *(uint32_t*)instr_union.instr, (void *) badvaddr); return PF_ACCESS_EXEC; } @@ -136,4 +234,5 @@ inst, (void *) badvaddr); } +#endif /** Handles "data abort" exception (load or store at invalid address). @@ -145,10 +244,49 @@ void data_abort(unsigned int exc_no, istate_t *istate) { - fault_status_t fsr __attribute__ ((unused)) = - read_fault_status_register(); - uintptr_t badvaddr = read_fault_address_register(); - - pf_access_t access = get_memory_access_type(istate->pc, badvaddr); - + const uintptr_t badvaddr = read_data_fault_address_register(); + const fault_status_t fsr = read_data_fault_status_register(); + const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK; + + switch (source) { + case DFSR_SOURCE_TRANSLATION_L1: + case DFSR_SOURCE_TRANSLATION_L2: + case DFSR_SOURCE_PERMISSION_L1: + case DFSR_SOURCE_PERMISSION_L2: + /* Page fault is handled further down */ + break; + case DFSR_SOURCE_ALIGN: + case DFSR_SOURCE_CACHE_MAINTENANCE: + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1: + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2: + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1: + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2: + case DFSR_SOURCE_ACCESS_FLAG_L1: + case DFSR_SOURCE_ACCESS_FLAG_L2: + case DFSR_SOURCE_DOMAIN_L1: + case DFSR_SOURCE_DOMAIN_L2: + case DFSR_SOURCE_DEBUG: + case DFSR_SOURCE_SYNC_EXTERNAL: + case DFSR_SOURCE_TLB_CONFLICT: + case DFSR_SOURCE_LOCKDOWN: + case DFSR_SOURCE_COPROCESSOR: + case DFSR_SOURCE_SYNC_PARITY: + case DFSR_SOURCE_ASYNC_EXTERNAL: + case DFSR_SOURCE_ASYNC_PARITY: + case DFSR_SOURCE_MASK: + /* Weird abort stuff */ + fault_if_from_uspace(istate, "Unhandled abort %s at address: " + "%#x.", dfsr_source_to_str(source), badvaddr); + panic("Unhandled abort %s at address: %#x.", + dfsr_source_to_str(source), badvaddr); + } + +#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a) + const pf_access_t access = + fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ; +#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) + const pf_access_t access = get_memory_access_type(istate->pc, badvaddr); +#else +#error "Unsupported architecture" +#endif as_page_fault(badvaddr, access, istate); }