Index: Makefile.config
===================================================================
--- Makefile.config	(revision 0172ebaa7b25d1de67dbebe413b28e7ad722e43f)
+++ Makefile.config	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
@@ -37,9 +37,9 @@
 
 CONFIG_USERSPACE = n
-CONFIG_TEST =
+#CONFIG_TEST =
 #CONFIG_TEST = synch/rwlock1
 #CONFIG_TEST = synch/rwlock2
 #CONFIG_TEST = synch/rwlock3
-#CONFIG_TEST = synch/rwlock4
+CONFIG_TEST = synch/rwlock4
 #CONFIG_TEST = synch/rwlock5
 #CONFIG_TEST = synch/semaphore1
Index: arch/ia32/include/atomic.h
===================================================================
--- arch/ia32/include/atomic.h	(revision 0172ebaa7b25d1de67dbebe413b28e7ad722e43f)
+++ arch/ia32/include/atomic.h	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
@@ -36,7 +36,7 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock incl %0\n" : "=m" (*val));
+	__asm__ volatile ("lock incl %0\n" : "+m" (*val));
 #else
-	__asm__ volatile ("incl %0\n" : "=m" (*val));
+	__asm__ volatile ("incl %0\n" : "+m" (*val));
 #endif /* CONFIG_SMP */
 }
@@ -44,9 +44,38 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock decl %0\n" : "=m" (*val));
+	__asm__ volatile ("lock decl %0\n" : "+m" (*val));
 #else
-	__asm__ volatile ("decl %0\n" : "=m" (*val));
+	__asm__ volatile ("decl %0\n" : "+m" (*val));
 #endif /* CONFIG_SMP */
 }
+
+static inline atomic_t atomic_inc_pre(atomic_t *val) 
+{
+	atomic_t r;
+	__asm__ volatile (
+		"movl $1,%0;"
+		"lock xaddl %0,%1;"
+		: "=r"(r), "+m" (*val)
+	);
+	return r;
+}
+
+
+
+static inline atomic_t atomic_dec_pre(atomic_t *val) 
+{
+	atomic_t r;
+	__asm__ volatile (
+		"movl $-1,%0;"
+		"lock xaddl %0,%1;"
+		: "=r"(r), "+m" (*val)
+	);
+	return r;
+}
+
+#define atomic_inc_post(val) (atomic_inc_pre(val)+1)
+#define atomic_dec_post(val) (atomic_dec_pre(val)-1)
+
+
 
 static inline int test_and_set(volatile int *val) {
@@ -56,5 +85,5 @@
 		"movl $1, %0\n"
 		"xchgl %0, %1\n"
-		: "=r" (v),"=m" (*val)
+		: "=r" (v),"+m" (*val)
 	);
 	
Index: arch/ia64/include/atomic.h
===================================================================
--- arch/ia64/include/atomic.h	(revision 0172ebaa7b25d1de67dbebe413b28e7ad722e43f)
+++ arch/ia64/include/atomic.h	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
@@ -38,7 +38,7 @@
 	atomic_t v;
 
-/*	
- *	__asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "=m" (val) : "i" (imm));
- */
+	
+ 	__asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (*val) : "i" (imm));
+ 
  	*val += imm;
 	
@@ -46,6 +46,17 @@
 }
 
-static inline atomic_t atomic_inc(atomic_t *val) { return atomic_add(val, 1); }
-static inline atomic_t atomic_dec(atomic_t *val) { return atomic_add(val, -1); }
+static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); }
+static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
+
+
+static inline atomic_t atomic_inc_pre(atomic_t *val) { return atomic_add(val, 1); }
+static inline atomic_t atomic_dec_pre(atomic_t *val) { return atomic_add(val, -1); }
+
+
+static inline atomic_t atomic_inc_post(atomic_t *val) { return atomic_add(val, 1)+1; }
+static inline atomic_t atomic_dec_post(atomic_t *val) { return atomic_add(val, -1)-1; }
+
+
+
 
 #endif
Index: arch/ia64/src/ivt.S
===================================================================
--- arch/ia64/src/ivt.S	(revision 0172ebaa7b25d1de67dbebe413b28e7ad722e43f)
+++ arch/ia64/src/ivt.S	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
@@ -1,5 +1,4 @@
 #
 # Copyright (C) 2005 Jakub Vana
-# Copyright (C) 2005 Jakub Jermar
 # All rights reserved.
 #
@@ -29,5 +28,4 @@
 
 #include <arch/stack.h>
-#include <arch/register.h>
 
 #define STACK_ITEMS		12
@@ -107,5 +105,5 @@
 	
 	/* assume kernel backing store */
-	/* mov ar.bspstore = r28 ;; */
+	mov ar.bspstore = r28 ;;
 	
 	mov r29 = ar.bsp
@@ -147,6 +145,6 @@
 	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
-	/* mov ar.bspstore = r28 ;; */	/* (step 4) */
-	/* mov ar.rnat = r27 */		/* (step 5) */
+	mov ar.bspstore = r28 ;;	/* (step 4) */
+	mov ar.rnat = r27		/* (step 5) */
 
 	mov ar.pfs = r25		/* (step 6) */
@@ -192,5 +190,5 @@
 
     /* 6. switch to bank 1 and reenable PSR.ic */
-	ssm PSR_IC_MASK
+	ssm 0x2000
 	bsw.1 ;;
 	srlz.d
@@ -248,9 +246,4 @@
     
     /* 9. skipped (will not enable interrupts) */
-	/*
-    	 * ssm PSR_I_MASK
-	 * ;;
-	 * srlz.d
-	 */
 
     /* 10. call handler */
@@ -262,9 +255,4 @@
 	
     /* 12. skipped (will not disable interrupts) */
-	/*
-    	 * rsm PSR_I_MASK
-	 * ;;
-	 * srlz.d
-	 */
 
     /* 13. restore general and floating-point registers */
@@ -320,5 +308,5 @@
 	
     /* 15. disable PSR.ic and switch to bank 0 */
-	rsm PSR_IC_MASK
+	rsm 0x2000
 	bsw.0 ;;
 	srlz.d
Index: arch/mips32/include/atomic.h
===================================================================
--- arch/mips32/include/atomic.h	(revision 0172ebaa7b25d1de67dbebe413b28e7ad722e43f)
+++ arch/mips32/include/atomic.h	(revision 73a4bab884b4a69008533a1891f2ac2c4278ce2c)
@@ -35,4 +35,11 @@
 #define atomic_dec(x)	(a_sub(x,1))
 
+#define atomic_inc_pre(x) (a_add(x,1)-1)
+#define atomic_dec_pre(x) (a_sub(x,1)+1)
+
+#define atomic_inc_post(x) (a_add(x,1))
+#define atomic_dec_post(x) (a_sub(x,1))
+
+
 typedef volatile __u32 atomic_t;
 
@@ -45,4 +52,7 @@
  * of the variable to a special register and if another process writes to
  * the same location, the SC (store-conditional) instruction fails.
+ 
+ Returns (*val)+i
+ 
  */
 static inline atomic_t a_add(atomic_t *val, int i)
@@ -73,4 +83,7 @@
  *
  * Implemented in the same manner as a_add, except we substract the value.
+
+ Returns (*val)-i
+
  */
 static inline atomic_t a_sub(atomic_t *val, int i)