Index: kernel/Makefile =================================================================== --- kernel/Makefile (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/Makefile (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -91,5 +91,5 @@ COMMON_CFLAGS = $(INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \ - -ffreestanding -nostdlib -nostdinc \ + -ffreestanding -nostdlib \ -fexec-charset=UTF-8 -finput-charset=UTF-8 -fno-common \ -fdebug-prefix-map=$(realpath $(ROOT_PATH))=. Index: kernel/arch/abs32le/Makefile.inc =================================================================== --- kernel/arch/abs32le/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/abs32le/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -49,4 +49,5 @@ arch/$(KARCH)/src/abs32le.c \ arch/$(KARCH)/src/userspace.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/cpu/cpu.c \ arch/$(KARCH)/src/smp/smp.c \ Index: kernel/arch/abs32le/include/arch/barrier.h =================================================================== --- kernel/arch/abs32le/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup abs32le - * @{ - */ -/** @file - */ - -#ifndef KERN_abs32le_BARRIER_H_ -#define KERN_abs32le_BARRIER_H_ - -/* - * Provisions are made to prevent compiler from reordering instructions itself. - */ - -#define CS_ENTER_BARRIER() -#define CS_LEAVE_BARRIER() - -#define memory_barrier() -#define read_barrier() -#define write_barrier() - -#ifdef KERNEL - -#define smc_coherence(addr, size) - -#endif /* KERNEL*/ - -#endif - -/** @} - */ Index: kernel/arch/abs32le/src/smc.c =================================================================== --- kernel/arch/abs32le/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/abs32le/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void smc_coherence(void *a, size_t l) +{ + compiler_barrier(); +} + Index: kernel/arch/amd64/Makefile.inc =================================================================== --- kernel/arch/amd64/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/amd64/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -79,4 +79,5 @@ arch/$(KARCH)/src/proc/thread.c \ arch/$(KARCH)/src/userspace.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/syscall.c Index: kernel/arch/amd64/include/arch/barrier.h =================================================================== --- kernel/arch/amd64/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ (revision ) @@ -1,1 +1,0 @@ -../../../ia32/include/arch/barrier.h Index: kernel/arch/amd64/src/smc.c =================================================================== --- kernel/arch/amd64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/amd64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void smc_coherence(void *a, size_t l) +{ + compiler_barrier(); +} + Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -57,4 +57,5 @@ arch/$(KARCH)/src/exception.c \ arch/$(KARCH)/src/userspace.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/debug/stacktrace.c \ arch/$(KARCH)/src/debug/stacktrace_asm.S \ Index: kernel/arch/arm32/include/arch/barrier.h =================================================================== --- kernel/arch/arm32/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/include/arch/barrier.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -37,16 +37,10 @@ #define KERN_arm32_BARRIER_H_ -#ifdef KERNEL #include #include #include -#else -#include -#endif - -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") #if defined PROCESSOR_ARCH_armv7_a + /* * ARMv7 uses instructions for memory barriers see ARM Architecture reference @@ -57,9 +51,10 @@ * and functionality on armv7 architecture. */ -#define memory_barrier() asm volatile ("dmb" ::: "memory") -#define read_barrier() asm volatile ("dsb" ::: "memory") -#define write_barrier() asm volatile ("dsb st" ::: "memory") -#define inst_barrier() asm volatile ("isb" ::: "memory") -#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL +#define dmb() asm volatile ("dmb" ::: "memory") +#define dsb() asm volatile ("dsb" ::: "memory") +#define isb() asm volatile ("isb" ::: "memory") + +#elif defined PROCESSOR_ARCH_armv6 + /* * ARMv6 introduced user access of the following commands: @@ -75,66 +70,15 @@ * CP15 implementation is mandatory only for armv6+. */ -#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a) -#define memory_barrier() CP15DMB_write(0) +#define dmb() CP15DMB_write(0) +#define dsb() CP15DSB_write(0) +#define isb() CP15ISB_write(0) + #else -#define memory_barrier() CP15DSB_write(0) -#endif -#define read_barrier() CP15DSB_write(0) -#define write_barrier() read_barrier() -#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a) -#define inst_barrier() CP15ISB_write(0) -#else -#define inst_barrier() -#endif -#else -/* - * Older manuals mention syscalls as a way to implement cache coherency and - * barriers. See for example ARM Architecture Reference Manual Version D - * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28) - */ -// TODO implement on per PROCESSOR basis or via syscalls -#define memory_barrier() asm volatile ("" ::: "memory") -#define read_barrier() asm volatile ("" ::: "memory") -#define write_barrier() asm volatile ("" ::: "memory") -#define inst_barrier() asm volatile ("" ::: "memory") -#endif -#ifdef KERNEL - -/* - * There are multiple ways ICache can be implemented on ARM machines. Namely - * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference - * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum - * compatibility across processors, ARM recommends that operating systems target - * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, - * and do not assume the presence of the IVIPT extension. Software that relies - * on the IVIPT extension might fail in an unpredictable way on an ARMv7 - * implementation that does not include the IVIPT extension." (7.2.6 p. 245). - * Only PIPT invalidates cache for all VA aliases if one block is invalidated. - * - * @note: Supporting ASID and VMID tagged VIVT may need to add ICache - * maintenance to other places than just smc. - */ - -#ifdef KERNEL - -/* - * @note: Cache type register is not available in uspace. We would need - * to export the cache line value, or use syscall for uspace smc_coherence - */ -#define smc_coherence(a, l) \ -do { \ - for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \ - addr += CP15_C7_MVA_ALIGN) \ - dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \ - write_barrier(); /* Wait for completion */\ - icache_invalidate();\ - write_barrier();\ - inst_barrier(); /* Wait for Inst refetch */\ -} while (0) +#define dmb() CP15DSB_write(0) +#define dsb() CP15DSB_write(0) +#define isb() #endif - -#endif /* KERNEL */ #endif Index: kernel/arch/arm32/include/arch/mm/page.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/include/arch/mm/page.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -41,4 +41,5 @@ #include #include +#include #include #include Index: kernel/arch/arm32/include/arch/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -37,4 +37,6 @@ #ifndef KERN_arm32_PAGE_armv4_H_ #define KERN_arm32_PAGE_armv4_H_ + +#include #ifndef KERN_arm32_PAGE_H_ Index: kernel/arch/arm32/src/atomic.c =================================================================== --- kernel/arch/arm32/src/atomic.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/src/atomic.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -35,4 +35,5 @@ #include +#include @@ -64,4 +65,9 @@ return cur_val; +} + +void __sync_synchronize(void) +{ + dsb(); } Index: kernel/arch/arm32/src/mm/tlb.c =================================================================== --- kernel/arch/arm32/src/mm/tlb.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/arm32/src/mm/tlb.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -41,4 +41,5 @@ #include #include +#include /** Invalidate all entries in TLB. @@ -59,6 +60,6 @@ * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375 */ - read_barrier(); - inst_barrier(); + dsb(); + isb(); } @@ -105,6 +106,6 @@ * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375 */ - read_barrier(); - inst_barrier(); + dsb(); + isb(); } Index: kernel/arch/arm32/src/smc.c =================================================================== --- kernel/arch/arm32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/arm32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* + * There are multiple ways ICache can be implemented on ARM machines. Namely + * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference + * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum + * compatibility across processors, ARM recommends that operating systems target + * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, + * and do not assume the presence of the IVIPT extension. Software that relies + * on the IVIPT extension might fail in an unpredictable way on an ARMv7 + * implementation that does not include the IVIPT extension." (7.2.6 p. 245). + * Only PIPT invalidates cache for all VA aliases if one block is invalidated. + * + * @note: Supporting ASID and VMID tagged VIVT may need to add ICache + * maintenance to other places than just smc. + */ + +// TODO: Determine CP15_C7_MVA_ALIGN dynamically + +void smc_coherence(void *a, size_t l) +{ + uintptr_t end = (uintptr_t) a + l; + uintptr_t begin = ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN); + + for (uintptr_t addr = begin; addr < end; addr += CP15_C7_MVA_ALIGN) { + dcache_clean_mva_pou(addr); + } + + /* Wait for completion */ + dsb(); + + icache_invalidate(); + dsb(); + /* Wait for Inst refetch */ + isb(); +} + Index: kernel/arch/ia32/Makefile.inc =================================================================== --- kernel/arch/ia32/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/ia32/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -87,4 +87,5 @@ arch/$(KARCH)/src/pm.c \ arch/$(KARCH)/src/userspace.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/cpu/cpu.c \ arch/$(KARCH)/src/mm/km.c \ Index: kernel/arch/ia32/include/arch/barrier.h =================================================================== --- kernel/arch/ia32/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ (revision ) @@ -1,115 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup ia32 - * @{ - */ -/** @file - */ - -#ifndef KERN_ia32_BARRIER_H_ -#define KERN_ia32_BARRIER_H_ - -#include - -/* - * NOTE: - * No barriers for critical section (i.e. spinlock) on IA-32 are needed: - * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction - * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers - */ - -/* - * Provisions are made to prevent compiler from reordering instructions itself. - */ - -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") - -NO_TRACE static inline void cpuid_serialization(void) -{ -#ifndef __PIC__ - asm volatile ( - "xorl %%eax, %%eax\n" - "cpuid\n" - ::: "eax", "ebx", "ecx", "edx", "memory" - ); -#else - /* Must not clobber PIC register ebx */ - asm volatile ( - "movl %%ebx, %%esi\n" - "xorl %%eax, %%eax\n" - "cpuid\n" - "movl %%esi, %%ebx\n" - ::: "eax", "ecx", "edx", "esi", "memory" - ); -#endif -} - -#if defined(CONFIG_FENCES_P4) -#define memory_barrier() asm volatile ("mfence\n" ::: "memory") -#define read_barrier() asm volatile ("lfence\n" ::: "memory") -#ifdef CONFIG_WEAK_MEMORY -#define write_barrier() asm volatile ("sfence\n" ::: "memory") -#else -#define write_barrier() asm volatile ("" ::: "memory"); -#endif -#elif defined(CONFIG_FENCES_P3) -#define memory_barrier() cpuid_serialization() -#define read_barrier() cpuid_serialization() -#ifdef CONFIG_WEAK_MEMORY -#define write_barrier() asm volatile ("sfence\n" ::: "memory") -#else -#define write_barrier() asm volatile ("" ::: "memory"); -#endif -#else -#define memory_barrier() cpuid_serialization() -#define read_barrier() cpuid_serialization() -#ifdef CONFIG_WEAK_MEMORY -#define write_barrier() cpuid_serialization() -#else -#define write_barrier() asm volatile ("" ::: "memory"); -#endif -#endif - -#ifdef KERNEL - -/* - * On ia32, the hardware takes care about instruction and data cache coherence, - * even on SMP systems. We issue a write barrier to be sure that writes - * queueing in the store buffer drain to the memory (even though it would be - * sufficient for them to drain to the D-cache). - */ -#define smc_coherence(a, l) write_barrier() - -#endif /* KERNEL */ - -#endif - -/** @} - */ Index: kernel/arch/ia32/src/smc.c =================================================================== --- kernel/arch/ia32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/ia32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void smc_coherence(void *a, size_t l) +{ + compiler_barrier(); +} + Index: kernel/arch/ia64/Makefile.inc =================================================================== --- kernel/arch/ia64/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/ia64/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -58,4 +58,5 @@ arch/$(KARCH)/src/proc/scheduler.c \ arch/$(KARCH)/src/ddi/ddi.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/smp/smp.c \ arch/$(KARCH)/src/smp/smp_call.c \ Index: kernel/arch/ia64/include/arch/barrier.h =================================================================== --- kernel/arch/ia64/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/ia64/include/arch/barrier.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -36,13 +36,5 @@ #define KERN_ia64_BARRIER_H_ -/* - * TODO: Implement true IA-64 memory barriers for macros below. - */ -#define CS_ENTER_BARRIER() memory_barrier() -#define CS_LEAVE_BARRIER() memory_barrier() - -#define memory_barrier() asm volatile ("mf\n" ::: "memory") -#define read_barrier() memory_barrier() -#define write_barrier() memory_barrier() +#define mf() asm volatile ("mf\n" ::: "memory") #define srlz_i() \ @@ -56,18 +48,4 @@ asm volatile (";; sync.i\n" ::: "memory") -#ifdef KERNEL - -#define FC_INVAL_MIN 32 -#define smc_coherence(a, l) \ -{ \ - unsigned long i; \ - for (i = 0; i < (l); i += FC_INVAL_MIN) \ - fc_i((void *)(a) + i); \ - sync_i(); \ - srlz_i(); \ -} - -#endif /* KERNEL */ - #endif Index: kernel/arch/ia64/include/arch/cpu.h =================================================================== --- kernel/arch/ia64/include/arch/cpu.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/ia64/include/arch/cpu.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -38,4 +38,5 @@ #include #include +#include #include #include Index: kernel/arch/ia64/src/mm/vhpt.c =================================================================== --- kernel/arch/ia64/src/mm/vhpt.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/ia64/src/mm/vhpt.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -34,4 +34,5 @@ #include +#include #include #include Index: kernel/arch/ia64/src/smc.c =================================================================== --- kernel/arch/ia64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/ia64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#define FC_INVAL_MIN 32 + +void smc_coherence(void *a, size_t l) +{ + unsigned long i; + for (i = 0; i < (l); i += FC_INVAL_MIN) + fc_i(a + i); + sync_i(); + srlz_i(); +} + Index: kernel/arch/mips32/Makefile.inc =================================================================== --- kernel/arch/mips32/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/mips32/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -71,4 +71,5 @@ arch/$(KARCH)/src/mm/as.c \ arch/$(KARCH)/src/fpu_context.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/smp/smp.c \ arch/$(KARCH)/src/smp/smp_call.c \ Index: kernel/arch/mips32/include/arch/barrier.h =================================================================== --- kernel/arch/mips32/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ (revision ) @@ -1,57 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup mips32 - * @{ - */ -/** @file - */ - -#ifndef KERN_mips32_BARRIER_H_ -#define KERN_mips32_BARRIER_H_ - -/* - * TODO: implement true MIPS memory barriers for macros below. - */ -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") - -#define memory_barrier() asm volatile ("" ::: "memory") -#define read_barrier() asm volatile ("" ::: "memory") -#define write_barrier() asm volatile ("" ::: "memory") - -#ifdef KERNEL - -#define smc_coherence(a, l) - -#endif /* KERNEL */ - -#endif - -/** @} - */ Index: kernel/arch/mips32/src/debugger.c =================================================================== --- kernel/arch/mips32/src/debugger.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/mips32/src/debugger.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -147,4 +147,10 @@ } +static inline void write_inst(uintptr_t addr, uint32_t inst) +{ + *((uint32_t *) addr) = inst; + smc_coherence((uint32_t *) addr, 4); +} + #ifdef CONFIG_KCONSOLE @@ -212,6 +218,5 @@ /* Set breakpoint */ - *((sysarg_t *) cur->address) = 0x0d; - smc_coherence(cur->address, 4); + write_inst(cur->address, 0x0d); irq_spinlock_unlock(&bkpoint_lock, true); @@ -245,8 +250,6 @@ } - ((uint32_t *) cur->address)[0] = cur->instruction; - smc_coherence(((uint32_t *) cur->address)[0], 4); - ((uint32_t *) cur->address)[1] = cur->nextinstruction; - smc_coherence(((uint32_t *) cur->address)[1], 4); + write_inst(cur->address, cur->instruction); + write_inst(cur->address + 4, cur->nextinstruction); cur->address = (uintptr_t) NULL; @@ -357,10 +360,8 @@ if (cur->flags & BKPOINT_REINST) { /* Set breakpoint on first instruction */ - ((uint32_t *) cur->address)[0] = 0x0d; - smc_coherence(((uint32_t *)cur->address)[0], 4); + write_inst(cur->address, 0x0d); /* Return back the second */ - ((uint32_t *) cur->address)[1] = cur->nextinstruction; - smc_coherence(((uint32_t *) cur->address)[1], 4); + write_inst(cur->address + 4, cur->nextinstruction); cur->flags &= ~BKPOINT_REINST; @@ -379,10 +380,9 @@ /* Return first instruction back */ - ((uint32_t *)cur->address)[0] = cur->instruction; - smc_coherence(cur->address, 4); + write_inst(cur->address, cur->instruction); if (!(cur->flags & BKPOINT_ONESHOT)) { /* Set Breakpoint on next instruction */ - ((uint32_t *)cur->address)[1] = 0x0d; + write_inst(cur->address + 4, 0x0d); cur->flags |= BKPOINT_REINST; } Index: kernel/arch/mips32/src/smc.c =================================================================== --- kernel/arch/mips32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/mips32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void smc_coherence(void *a, size_t l) +{ + // TODO + compiler_barrier(); +} + Index: kernel/arch/ppc32/Makefile.inc =================================================================== --- kernel/arch/ppc32/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/ppc32/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -51,4 +51,5 @@ arch/$(KARCH)/src/cpu/cpu.c \ arch/$(KARCH)/src/proc/scheduler.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/mm/km.c \ arch/$(KARCH)/src/mm/as.c \ Index: kernel/arch/ppc32/include/arch/barrier.h =================================================================== --- kernel/arch/ppc32/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ (revision ) @@ -1,90 +1,0 @@ -/* - * Copyright (c) 2005 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup ppc32 - * @{ - */ -/** @file - */ - -#ifndef KERN_ppc32_BARRIER_H_ -#define KERN_ppc32_BARRIER_H_ - -#include - -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") - -#define memory_barrier() asm volatile ("sync" ::: "memory") -#define read_barrier() asm volatile ("sync" ::: "memory") -#define write_barrier() asm volatile ("eieio" ::: "memory") - -#define instruction_barrier() \ - asm volatile ( \ - "sync\n" \ - "isync\n" \ - ) - -#ifdef KERNEL - -#define COHERENCE_INVAL_MIN 4 - -/* - * The IMB sequence used here is valid for all possible cache models - * on uniprocessor. SMP might require a different sequence. - * See PowerPC Programming Environment for 32-Bit Microprocessors, - * chapter 5.1.5.2 - */ - -NO_TRACE static inline void smc_coherence(void *addr, unsigned int len) -{ - unsigned int i; - - for (i = 0; i < len; i += COHERENCE_INVAL_MIN) - asm volatile ( - "dcbst 0, %[addr]\n" - :: [addr] "r" (addr + i) - ); - - memory_barrier(); - - for (i = 0; i < len; i += COHERENCE_INVAL_MIN) - asm volatile ( - "icbi 0, %[addr]\n" - :: [addr] "r" (addr + i) - ); - - instruction_barrier(); -} - -#endif /* KERNEL */ - -#endif - -/** @} - */ Index: kernel/arch/ppc32/src/smc.c =================================================================== --- kernel/arch/ppc32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/ppc32/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include + +#define COHERENCE_INVAL_MIN 4 + +/* + * The IMB sequence used here is valid for all possible cache models + * on uniprocessor. SMP might require a different sequence. + * See PowerPC Programming Environment for 32-Bit Microprocessors, + * chapter 5.1.5.2 + */ + +void smc_coherence(void *addr, size_t len) +{ + unsigned int i; + + for (i = 0; i < len; i += COHERENCE_INVAL_MIN) + asm volatile ( + "dcbst 0, %[addr]\n" + :: [addr] "r" (addr + i) + ); + + asm volatile ("sync" ::: "memory"); + + for (i = 0; i < len; i += COHERENCE_INVAL_MIN) + asm volatile ( + "icbi 0, %[addr]\n" + :: [addr] "r" (addr + i) + ); + + asm volatile ("sync" ::: "memory"); + asm volatile ("isync" ::: "memory"); +} + Index: kernel/arch/riscv64/Makefile.inc =================================================================== --- kernel/arch/riscv64/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/riscv64/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -47,4 +47,5 @@ arch/$(KARCH)/src/riscv64.c \ arch/$(KARCH)/src/userspace.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/cpu/cpu.c \ arch/$(KARCH)/src/mm/km.c \ Index: kernel/arch/riscv64/include/arch/barrier.h =================================================================== --- kernel/arch/riscv64/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2016 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup riscv64 - * @{ - */ -/** @file - */ - -#ifndef KERN_riscv64_BARRIER_H_ -#define KERN_riscv64_BARRIER_H_ - -#include - -// FIXME - -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") - -#define memory_barrier() asm volatile ("" ::: "memory") -#define read_barrier() asm volatile ("" ::: "memory") -#define write_barrier() asm volatile ("" ::: "memory") - -#ifdef KERNEL - -#define smc_coherence(addr, size) - -#endif /* KERNEL */ - -#endif - -/** @} - */ Index: kernel/arch/riscv64/src/smc.c =================================================================== --- kernel/arch/riscv64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/riscv64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void smc_coherence(void *a, size_t l) +{ + // TODO + compiler_barrier(); +} + Index: kernel/arch/sparc64/Makefile.inc =================================================================== --- kernel/arch/sparc64/Makefile.inc (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/sparc64/Makefile.inc (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -77,4 +77,5 @@ arch/$(KARCH)/src/proc/$(USARCH)/scheduler.c \ arch/$(KARCH)/src/proc/thread.c \ + arch/$(KARCH)/src/smc.c \ arch/$(KARCH)/src/trap/$(USARCH)/mmu.S \ arch/$(KARCH)/src/trap/$(USARCH)/trap_table.S \ Index: kernel/arch/sparc64/include/arch/barrier.h =================================================================== --- kernel/arch/sparc64/include/arch/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/sparc64/include/arch/barrier.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -38,45 +38,4 @@ #include -/* - * Our critical section barriers are prepared for the weakest RMO memory model. - */ -#define CS_ENTER_BARRIER() \ - asm volatile ( \ - "membar #LoadLoad | #LoadStore\n" \ - ::: "memory" \ - ) - -#define CS_LEAVE_BARRIER() \ - asm volatile ( \ - "membar #StoreStore\n" \ - "membar #LoadStore\n" \ - ::: "memory" \ - ) - -#define memory_barrier() \ - asm volatile ( \ - "membar #LoadLoad | #StoreStore\n" \ - ::: "memory" \ - ) - -#define read_barrier() \ - asm volatile ( \ - "membar #LoadLoad\n" \ - ::: "memory" \ - ) - -#define write_barrier() \ - asm volatile ( \ - "membar #StoreStore\n" \ - ::: "memory" \ - ) - -#define flush(a) \ - asm volatile ( \ - "flush %[reg]\n" \ - :: [reg] "r" ((a)) \ - : "memory" \ - ) - /** Flush Instruction pipeline. */ NO_TRACE static inline void flush_pipeline(void) @@ -110,31 +69,4 @@ } -#ifdef KERNEL - -#if defined(US) - -#define FLUSH_INVAL_MIN 4 - -#define smc_coherence(a, l) \ - do { \ - unsigned long i; \ - write_barrier(); \ - \ - for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ - flush((void *)(a) + i); \ - } while (0) - -#elif defined (US3) - -#define smc_coherence(a, l) \ - do { \ - write_barrier(); \ - flush_pipeline(); \ - } while (0) - -#endif /* defined(US3) */ - -#endif /* KERNEL */ - #endif Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -98,4 +98,5 @@ #include #include +#include #include #include Index: kernel/arch/sparc64/src/smc.c =================================================================== --- kernel/arch/sparc64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) +++ kernel/arch/sparc64/src/smc.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#if defined(US) + +#define FLUSH_INVAL_MIN 4 + +void smc_coherence(void *a, size_t l) +{ + asm volatile ("membar #StoreStore\n" ::: "memory"); + + for (size_t i = 0; i < l; i += FLUSH_INVAL_MIN) { + asm volatile ( + "flush %[reg]\n" + :: [reg] "r" (a + i) + : "memory" + ); + } +} + +#elif defined (US3) + + +void smc_coherence(void *a, size_t l) +{ + asm volatile ("membar #StoreStore\n" ::: "memory"); + + flush_pipeline(); +} + +#endif /* defined(US3) */ + Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c =================================================================== --- kernel/arch/sparc64/src/smp/sun4u/ipi.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/sparc64/src/smp/sun4u/ipi.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -34,4 +34,5 @@ #include +#include #include #include Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c =================================================================== --- kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -33,4 +33,5 @@ */ +#include #include #include Index: kernel/generic/include/barrier.h =================================================================== --- kernel/generic/include/barrier.h (revision 954c0240b720c64358bccbdcdcb035fdd5a6f347) +++ kernel/generic/include/barrier.h (revision 7328ff41dcbe15332d62c013417ec72bbb613ee6) @@ -30,10 +30,34 @@ #define KERN_COMPILER_BARRIER_H_ -#include +#include +#include -#define compiler_barrier() asm volatile ("" ::: "memory") +static inline void compiler_barrier(void) +{ + atomic_signal_fence(memory_order_seq_cst); +} + +static inline void memory_barrier(void) +{ + atomic_thread_fence(memory_order_seq_cst); +} + +static inline void read_barrier(void) +{ + atomic_thread_fence(memory_order_acquire); +} + +static inline void write_barrier(void) +{ + atomic_thread_fence(memory_order_release); +} + +#define CS_ENTER_BARRIER() atomic_thread_fence(memory_order_acquire) +#define CS_LEAVE_BARRIER() atomic_thread_fence(memory_order_release) /** Forces the compiler to access (ie load/store) the variable only once. */ #define ACCESS_ONCE(var) (*((volatile typeof(var)*)&(var))) +extern void smc_coherence(void *, size_t); + #endif /* KERN_COMPILER_BARRIER_H_ */