Index: kernel/arch/sparc64/Makefile.inc
===================================================================
--- kernel/arch/sparc64/Makefile.inc	(revision 7f7d64298fbfdc2ce850eb86156d829a4def23e6)
+++ kernel/arch/sparc64/Makefile.inc	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
@@ -77,4 +77,5 @@
 	arch/$(KARCH)/src/proc/$(USARCH)/scheduler.c \
 	arch/$(KARCH)/src/proc/thread.c \
+	arch/$(KARCH)/src/smc.c \
 	arch/$(KARCH)/src/trap/$(USARCH)/mmu.S \
 	arch/$(KARCH)/src/trap/$(USARCH)/trap_table.S \
Index: kernel/arch/sparc64/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc64/include/arch/barrier.h	(revision 7f7d64298fbfdc2ce850eb86156d829a4def23e6)
+++ kernel/arch/sparc64/include/arch/barrier.h	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
@@ -38,45 +38,4 @@
 #include <trace.h>
 
-/*
- * Our critical section barriers are prepared for the weakest RMO memory model.
- */
-#define CS_ENTER_BARRIER() \
-	asm volatile ( \
-		"membar #LoadLoad | #LoadStore\n" \
-		::: "memory" \
-	)
-
-#define CS_LEAVE_BARRIER() \
-	asm volatile ( \
-		"membar #StoreStore\n" \
-		"membar #LoadStore\n" \
-		::: "memory" \
-	)
-
-#define memory_barrier() \
-	asm volatile ( \
-		"membar #LoadLoad | #StoreStore\n" \
-		::: "memory" \
-	)
-
-#define read_barrier() \
-	asm volatile ( \
-		"membar #LoadLoad\n" \
-		::: "memory" \
-	)
-
-#define write_barrier() \
-	asm volatile ( \
-		"membar #StoreStore\n" \
-		::: "memory" \
-	)
-
-#define flush(a) \
-	asm volatile ( \
-		"flush %[reg]\n" \
-		:: [reg] "r" ((a)) \
-		: "memory" \
-	)
-
 /** Flush Instruction pipeline. */
 NO_TRACE static inline void flush_pipeline(void)
@@ -110,31 +69,4 @@
 }
 
-#ifdef KERNEL
-
-#if defined(US)
-
-#define FLUSH_INVAL_MIN  4
-
-#define smc_coherence(a, l) \
-	do { \
-		unsigned long i; \
-		write_barrier(); \
-		\
-		for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
-			flush((void *)(a) + i); \
-	} while (0)
-
-#elif defined (US3)
-
-#define smc_coherence(a, l) \
-	do { \
-		write_barrier(); \
-		flush_pipeline(); \
-	} while (0)
-
-#endif  /* defined(US3) */
-
-#endif	/* KERNEL */
-
 #endif
 
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 7f7d64298fbfdc2ce850eb86156d829a4def23e6)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
@@ -98,4 +98,5 @@
 #include <arch/mm/page.h>
 #include <arch/asm.h>
+#include <arch/barrier.h>
 #include <barrier.h>
 #include <typedefs.h>
Index: kernel/arch/sparc64/src/smc.c
===================================================================
--- kernel/arch/sparc64/src/smc.c	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
+++ kernel/arch/sparc64/src/smc.c	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <barrier.h>
+#include <arch/barrier.h>
+
+#if defined(US)
+
+#define FLUSH_INVAL_MIN  4
+
+void smc_coherence(void *a, size_t l)
+{
+	asm volatile ("membar #StoreStore\n" ::: "memory");
+
+	for (size_t i = 0; i < l; i += FLUSH_INVAL_MIN) {
+		asm volatile (
+		    "flush %[reg]\n"
+		    :: [reg] "r" (a + i)
+		    : "memory"
+		);
+	}
+}
+
+#elif defined (US3)
+
+
+void smc_coherence(void *a, size_t l)
+{
+	asm volatile ("membar #StoreStore\n" ::: "memory");
+
+	flush_pipeline();
+}
+
+#endif  /* defined(US3) */
+
Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision 7f7d64298fbfdc2ce850eb86156d829a4def23e6)
+++ kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
@@ -34,4 +34,5 @@
 
 #include <smp/ipi.h>
+#include <arch/barrier.h>
 #include <arch/smp/sun4u/ipi.h>
 #include <assert.h>
Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/sun4u/interrupt.c	(revision 7f7d64298fbfdc2ce850eb86156d829a4def23e6)
+++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c	(revision 7328ff41dcbe15332d62c013417ec72bbb613ee6)
@@ -33,4 +33,5 @@
  */
 
+#include <arch/barrier.h>
 #include <arch/interrupt.h>
 #include <arch/sparc64.h>